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* Add testEddie Hung2019-06-201-0/+11
* Add proper test for SV-style arraysClifford Wolf2019-06-201-0/+16
* Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-191-0/+22
* Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
* Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-0/+16
* Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...Clifford Wolf2019-06-071-1/+2
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| * SystemVerilog support for implicit named port connectionstux32019-06-061-1/+2
* | Added tests for attributesMaciej Kurc2019-06-039-0/+219
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* Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-0/+4
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| * Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-0/+4
* | Add actual wandwor test that is part of "make test"Clifford Wolf2019-05-281-0/+36
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* Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
* Add test case from #997Clifford Wolf2019-05-071-0/+12
* Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-063-0/+32
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| * Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-031-0/+9
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| | * Add peepopt_muldiv, fixes #930Clifford Wolf2019-04-301-0/+9
| * | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-031-0/+22
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| | * | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+22
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| * / Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-011-0/+1
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* / Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
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* Add retime testEddie Hung2019-04-051-0/+6
* fix local name resolution in prefix constructsZachary Snow2019-03-181-0/+56
* Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-0/+19
* Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-041-0/+1
* Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-251-1/+0
* Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+2
* Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-171-0/+26
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| * Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-151-0/+26
* | Extend testcaseEddie Hung2019-02-061-2/+34
* | Add testcaseEddie Hung2019-02-061-0/+10
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* Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-181-90/+0
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+17
* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+76
* Fix tests/simple/specify.vClifford Wolf2018-03-271-2/+2
* First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-0/+31
* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-291-32/+0
* $size() now works correctly for all cases!Udi Finkelstein2017-09-261-5/+11
* $size() seems to work now with or without the optional parameter.Udi Finkelstein2017-09-261-8/+18
* Added $bits() for memories as well.Udi Finkelstein2017-09-261-6/+5
* $size() now works with memories as well!Udi Finkelstein2017-09-261-2/+4
* Add $size() function. At the moment it works only on expressions, not on memo...Udi Finkelstein2017-09-261-0/+15
* Squelch trailing whitespaceLarry Doolittle2017-04-121-1/+1
* Fixed typo in tests/simple/arraycells.vClifford Wolf2017-01-041-1/+1
* Added support for hierarchical defparamsClifford Wolf2016-11-151-0/+23
* Add optional SEED=n command line option to Makefile, and -S n command line op...Eric Smith2016-09-221-1/+12
* Fixed bug with memories that do not have a down-to-zero data widthClifford Wolf2016-08-221-0/+30
* Added another mem2reg test caseClifford Wolf2016-08-211-0/+11
* Another bugfix in mem2reg codeClifford Wolf2016-08-211-0/+22
* Fixed mem assignment in left-hand-side concatenationClifford Wolf2016-07-081-0/+13
* Fixed init issue in mem2reg_test2 test caseClifford Wolf2016-06-171-2/+6