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* ABC9: Cell Port Bug Patch (#3670)Benjamin Barzen2023-04-222-0/+16
| | | | | | | | | | | | | | | | | * ABC9: RAMB36E1 Bug Patch * Add simplified testcase * Also fix xaiger writer for under-width output ports * Remove old testcase * Missing top-level input port * Fix tabs --------- Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* add additional dff and lutram testsMiodrag Milanovic2023-04-062-0/+57
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* add test for CCU2DMiodrag Milanovic2023-04-061-0/+10
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* Update testsMiodrag Milanovic2023-03-207-16/+16
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* fabulous: Add support for mapping carry chainsgatecat2023-02-271-0/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Genericising bug1836.ysKrystalDelusion2023-02-211-20/+12
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* bug3205.ys removedKrystalDelusion2023-02-211-57/+0
| | | | Made redundant by TDP test(s) in memories.ys
* Removing extra `default_nettype` linesKrystalDelusion2023-02-211-2/+0
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* Fix for sync_ram_sdp not being final moduleKrystalDelusion2023-02-211-1/+1
| | | | Explicitly declare -top in synth_intel_alm.
* Tests for ram_style = "huge"KrystalDelusion2023-02-214-0/+219
| | | | iCE40 SPRAM and Xilinx URAM
* Testing TDP synth mappingKrystalDelusion2023-02-213-0/+49
| | | | | New common sync_ram_tdp. Used in ecp5 and gatemate mem*.ys.
* Asymmetric port ram tests with XilinxKrystalDelusion2023-02-213-0/+193
| | | | Uses verilog code from User Guide 901 (2021.1)
* Addings tests for #1836 and #3205KrystalDelusion2023-02-213-0/+120
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* fabulous: Allow adding extra custom prims and map rulesgatecat2022-11-173-0/+21
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: improvements to the passgatecat2022-11-177-0/+141
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Reenable existing equiv_opt testsJannis Harder2022-10-072-3/+3
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* Fix tests for check in equiv_optJannis Harder2022-10-075-7/+17
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* support file locations containing spacesMiodrag Milanovic2022-08-081-0/+1
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* gatemate: Add test for LUT tree mappinggatecat2022-06-273-0/+813
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* efinix: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-12/+1
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* ice40: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-56/+0
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* xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-46/+15
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* nexus: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-2/+2
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* ecp5: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-135/+18
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* intel_alm: M10K write-enable is negative-trueLofty2022-03-091-1/+2
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* gowin: Fix LUT RAM inference, add more models.Marcelina Kościelnicka2022-02-091-3/+2
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* anlogic: support BRAM mappingIcenowy Zheng2021-12-172-1/+14
| | | | | | | | | | | Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Fix the tests we just brokeClaire Xenia Wolf2021-12-101-2/+2
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
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* synth_gatemate: Update passPatrick Urban2021-11-131-4/+8
| | | | | | * remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style
* synth_gatemate: Apply new test practice with assert-maxPatrick Urban2021-11-137-12/+12
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* synth_gatemate: Fix fsm testPatrick Urban2021-11-131-2/+2
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* Allow initial blocks to be disabled during testsPatrick Urban2021-11-136-4/+20
| | | | Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
* synth_gatemate: Initial implementationPatrick Urban2021-11-1314-0/+337
| | | | Signed-off-by: Patrick Urban <patrick.urban@web.de>
* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-092-3/+3
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* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-2/+3
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-0/+7
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-201-1/+2
| | | | | | | | | * deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests
* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-112-78/+156
| | | | | | | | | | These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine.
* Add v2 memory cells.Marcelina Kościelnicka2021-08-112-25/+25
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* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-0/+24
| | | | Fixes #2061.
* Fix files with CRLF line endingsClaire Xenia Wolf2021-06-093-73/+73
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* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-254-17/+14
| | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
* intel_alm: Fix illegal carry chainsgatecat2021-05-152-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add global buffer insertiongatecat2021-05-1513-41/+41
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add IO buffer insertiongatecat2021-05-1513-39/+39
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-201-1/+1
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* quicklogic: ABC9 synthesisLofty2021-04-176-17/+17
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* quicklogic: Add .gitignore file for test outputs.Marcelina Kościelnicka2021-03-231-0/+4
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* quicklogic: PolarPro 3 supportLofty2021-03-1810-0/+262
| | | | | | | | Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
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