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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-08 03:52:50 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
| commit | 0a8eaca322a622610efe5a0d33d1cda83e4afa8c (patch) | |
| tree | 4d34ed2365f87d7a4c9da09de9fda0e1e00d101c /tests/arch | |
| parent | a04b025abff798f37d580a7d30084497d61d0fe0 (diff) | |
| download | yosys-0a8eaca322a622610efe5a0d33d1cda83e4afa8c.tar.gz yosys-0a8eaca322a622610efe5a0d33d1cda83e4afa8c.tar.bz2 yosys-0a8eaca322a622610efe5a0d33d1cda83e4afa8c.zip | |
nexus: Use `memory_libmap` pass.
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/nexus/blockram.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/nexus/blockram.ys b/tests/arch/nexus/blockram.ys index 9540136d5..a85b5141e 100644 --- a/tests/arch/nexus/blockram.ys +++ b/tests/arch/nexus/blockram.ys @@ -3,7 +3,7 @@ design -save read # Check that we use the right dual and single clock variants -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp synth_nexus -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:PDPSC16K @@ -11,7 +11,7 @@ select -assert-none t:PDPSC16K t:INV t:IB t:OB t:VLO t:VHI %% t:* %D design -reset read_verilog blockram_dc.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp_dc +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp_dc synth_nexus -top sync_ram_sdp_dc cd sync_ram_sdp_dc select -assert-count 1 t:PDP16K |