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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-03-06 02:21:53 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
| commit | 9d11575856e2345d2a6ae68f6b944d256d1e131a (patch) | |
| tree | 65656d85d93c9dc8acea4499287921633cdfdc31 /tests/arch | |
| parent | f4d1426229e0843d55a7ac2a10760acecf9c6710 (diff) | |
| download | yosys-9d11575856e2345d2a6ae68f6b944d256d1e131a.tar.gz yosys-9d11575856e2345d2a6ae68f6b944d256d1e131a.tar.bz2 yosys-9d11575856e2345d2a6ae68f6b944d256d1e131a.zip | |
efinix: Use `memory_libmap` pass.
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/efinix/lutram.ys | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/tests/arch/efinix/lutram.ys b/tests/arch/efinix/lutram.ys index dcf647ce0..8412d1389 100644 --- a/tests/arch/efinix/lutram.ys +++ b/tests/arch/efinix/lutram.ys @@ -1,17 +1,6 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r -proc -memory -nomap -equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Called with -verify and proof did fail! -#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter -sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt +synth_efinix cd lutram_1w1r select -assert-count 1 t:EFX_GBUFCE select -assert-count 1 t:EFX_RAM_5K |