ecp5: Use `memory_libmap` pass.

1 files changed, 18 insertions, 135 deletions

diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys
index 44651ba25..5cddcb952 100644
--- a/tests/arch/ecp5/memories.ys
+++ b/tests/arch/ecp5/memories.ys
@@ -1,11 +1,11 @@
 # ================================ RAM ================================
-# RAM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
+# RAM bits <= 18K; Data width <= 36; Address width <= 9: -> DP16KD
 
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
 hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:PDPW16KD
+select -assert-count 1 t:DP16KD
 
 ## With parameters
 
@@ -13,7 +13,7 @@ design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 0 t:PDPW16KD # too inefficient
+select -assert-count 0 t:DP16KD # too inefficient
 select -assert-count 9 t:TRELLIS_DPR16X4
 
 design -reset; read_verilog -defer ../common/blockram.v
@@ -21,28 +21,29 @@ chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:PDPW16KD
+select -assert-count 1 t:DP16KD
 
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "Block_RAM" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:PDPW16KD # any case works
+select -assert-count 1 t:DP16KD # any case works
 
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:PDPW16KD
+select -assert-count 0 t:DP16KD
+select -assert-count 9 t:TRELLIS_DPR16X4
 
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "registers" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
+select -assert-count 0 t:DP16KD # requested FFRAM explicitly
 select -assert-count 180 t:TRELLIS_FF
 
 design -reset; read_verilog -defer ../common/blockram.v
@@ -50,37 +51,9 @@ chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 hierarchy -top sync_ram_sdp
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
+select -assert-count 0 t:DP16KD # requested FFRAM explicitly
 select -assert-count 180 t:TRELLIS_FF
 
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_romstyle "ebr" m:memory
-synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set rom_block 1 m:memory
-synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "block_ram" m:memory
-synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set ram_block 1 m:memory
-synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
-
 # RAM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
 
 design -reset; read_verilog -defer ../common/blockram.v
@@ -141,7 +114,8 @@ chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
 hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:DP16KD
+select -assert-count 0 t:DP16KD # too inefficient
+select -assert-count 5 t:TRELLIS_DPR16X4
 
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
@@ -159,34 +133,6 @@ synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:DP16KD # requested FFRAM explicitly
 select -assert-count 90 t:TRELLIS_FF
 
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_romstyle "ebr" m:memory
-synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set rom_block 1 m:memory
-synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "block_ram" m:memory
-synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set ram_block 1 m:memory
-synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
-
 # RAM bits <= 64; Data width <= 4; Address width <= 4: -> DPR16X4
 
 design -reset; read_verilog -defer ../common/blockram.v
@@ -220,21 +166,14 @@ synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
 select -assert-count 68 t:TRELLIS_FF
 
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "distributed" m:memory
-synth_ecp5 -top sync_ram_sdp -nolutram; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested LUTRAM but LUTRAM is disabled
-
 # ================================ ROM ================================
-# ROM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
+# ROM bits <= 18K; Data width <= 36; Address width <= 9: -> DP16KD
 
 design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_rom
 hierarchy -top sync_rom
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:PDPW16KD
+select -assert-count 1 t:DP16KD
 
 ## With parameters
 
@@ -242,7 +181,7 @@ design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
 hierarchy -top sync_rom
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 0 t:PDPW16KD # too inefficient
+select -assert-count 0 t:DP16KD # too inefficient
 select -assert-min 18 t:LUT4
 
 design -reset; read_verilog -defer ../common/blockrom.v
@@ -250,21 +189,21 @@ chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
 hierarchy -top sync_rom
 setattr -set syn_romstyle "ebr" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:PDPW16KD
+select -assert-count 1 t:DP16KD
 
 design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
 hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:PDPW16KD
+select -assert-count 1 t:DP16KD
 
 design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
 hierarchy -top sync_rom
 setattr -set syn_romstyle "logic" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
+select -assert-count 0 t:DP16KD # requested LUTROM explicitly
 select -assert-min 18 t:LUT4
 
 design -reset; read_verilog -defer ../common/blockrom.v
@@ -272,37 +211,9 @@ chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
 hierarchy -top sync_rom
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
+select -assert-count 0 t:DP16KD # requested LUTROM explicitly
 select -assert-min 18 t:LUT4
 
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
-hierarchy -top sync_rom
-setattr -set syn_ramstyle "block_ram" m:memory
-synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
-hierarchy -top sync_rom
-setattr -set ram_block 1 m:memory
-synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
-hierarchy -top sync_rom
-setattr -set syn_ramstyle "block_rom" m:memory
-synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
-hierarchy -top sync_rom
-setattr -set rom_block 1 m:memory
-synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
-
 # ROM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
 
 design -reset; read_verilog -defer ../common/blockrom.v
@@ -349,31 +260,3 @@ setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:DP16KD # requested LUTROM explicitly
 select -assert-min 9 t:LUT4
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
-hierarchy -top sync_rom
-setattr -set syn_ramstyle "block_ram" m:memory
-synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
-hierarchy -top sync_rom
-setattr -set ram_block 1 m:memory
-synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
-hierarchy -top sync_rom
-setattr -set syn_ramstyle "block_rom" m:memory
-synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
-hierarchy -top sync_rom
-setattr -set rom_block 1 m:memory
-synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled