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| author | gatecat <gatecat@ds0.me> | 2022-11-16 13:35:37 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2022-11-17 13:34:58 +0100 |
| commit | b6467f080102834c82718470d706c4a848a6cb90 (patch) | |
| tree | 881c57508f3ae2964ec4f99100cbbd91fd06da61 /tests/arch | |
| parent | f111bbdf4006be9f108374c8591c682f02033a6f (diff) | |
| download | yosys-b6467f080102834c82718470d706c4a848a6cb90.tar.gz yosys-b6467f080102834c82718470d706c4a848a6cb90.tar.bz2 yosys-b6467f080102834c82718470d706c4a848a6cb90.zip | |
fabulous: Allow adding extra custom prims and map rules
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/fabulous/custom_map.v | 3 | ||||
| -rw-r--r-- | tests/arch/fabulous/custom_prims.v | 8 | ||||
| -rw-r--r-- | tests/arch/fabulous/customisation.ys | 10 |
3 files changed, 21 insertions, 0 deletions
diff --git a/tests/arch/fabulous/custom_map.v b/tests/arch/fabulous/custom_map.v new file mode 100644 index 000000000..1538e837b --- /dev/null +++ b/tests/arch/fabulous/custom_map.v @@ -0,0 +1,3 @@ +module AND(input [7:0] A, B, output [7:0] Y); + ALU #(.MODE("AND")) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y)); +endmodule diff --git a/tests/arch/fabulous/custom_prims.v b/tests/arch/fabulous/custom_prims.v new file mode 100644 index 000000000..4989188e2 --- /dev/null +++ b/tests/arch/fabulous/custom_prims.v @@ -0,0 +1,8 @@ +(* blackbox *) +module AND(input [7:0] A, B, output [7:0] Y); +endmodule + +(* blackbox *) +module ALU(input [7:0] A, B, output [7:0] Y); +parameter MODE = ""; +endmodule diff --git a/tests/arch/fabulous/customisation.ys b/tests/arch/fabulous/customisation.ys new file mode 100644 index 000000000..0e78d2e56 --- /dev/null +++ b/tests/arch/fabulous/customisation.ys @@ -0,0 +1,10 @@ +read_verilog <<EOT +module prim_test(input [7:0] a, b, output [7:0] q); + AND and_i (.A(a), .B(b), .Y(q)); +endmodule +EOT + +# Test adding custom primitives and techmap rules +synth_fabulous -top prim_test -extra-plib custom_prims.v -extra-map custom_map.v +cd prim_test +select -assert-count 1 t:ALU |