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| author | Jannis Harder <me@jix.one> | 2022-08-30 13:56:05 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-10-07 16:04:51 +0200 |
| commit | 0113f44faaa5778afd0fa3afbdbf12f33f2cea4e (patch) | |
| tree | 24af24f2dfb61ca607b99b5ffee73a54bf6a0fc2 /tests/arch | |
| parent | 81906aa627ed4a2d232a27a84e050bf86f2f83a6 (diff) | |
| download | yosys-0113f44faaa5778afd0fa3afbdbf12f33f2cea4e.tar.gz yosys-0113f44faaa5778afd0fa3afbdbf12f33f2cea4e.tar.bz2 yosys-0113f44faaa5778afd0fa3afbdbf12f33f2cea4e.zip | |
Reenable existing equiv_opt tests
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/ice40/bug1597.ys | 2 | ||||
| -rw-r--r-- | tests/arch/intel_alm/counter.ys | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/ice40/bug1597.ys b/tests/arch/ice40/bug1597.ys index 73bc18eb2..c1509cabc 100644 --- a/tests/arch/ice40/bug1597.ys +++ b/tests/arch/ice40/bug1597.ys @@ -70,4 +70,4 @@ EOT read_verilog -lib +/ice40/cells_sim.v hierarchy -top top flatten -equiv_opt -multiclock -map +/ice40/cells_sim.v synth_ice40 +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 diff --git a/tests/arch/intel_alm/counter.ys b/tests/arch/intel_alm/counter.ys index 56c9cabb3..0a5b9356a 100644 --- a/tests/arch/intel_alm/counter.ys +++ b/tests/arch/intel_alm/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check +equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -17,7 +17,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check +equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module |