opt_lut: Allow more than one -dlogic per cell type.

Fixes #2061.

1 files changed, 24 insertions, 0 deletions

diff --git a/tests/arch/ice40/bug2061.ys b/tests/arch/ice40/bug2061.ys
new file mode 100644
index 000000000..7dd7ee6a3
--- /dev/null
+++ b/tests/arch/ice40/bug2061.ys
@@ -0,0 +1,24 @@
+read_verilog <<EOT
+module top #(
+    parameter integer WIDTH = 12
+)(
+    output reg  [WIDTH:0] cnt,
+    input  wire clk,
+    input  wire rst
+);
+    wire last_n;
+
+    assign last_n = cnt[WIDTH];
+
+    always @(posedge clk or posedge rst)
+        if (rst)
+            cnt <= 0;
+        else
+            cnt <= last_n ? ( cnt + { (WIDTH+1){last_n} } ) : 13'h1aaa;
+
+endmodule
+EOT
+
+synth_ice40
+splitnets
+select -assert-count 12 t:SB_CARRY %co:+[CO] t:SB_LUT4 %ci:+[I3] %i