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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-09 06:13:34 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-09 09:04:34 +0100 |
| commit | f61f2a4078f36bbb1e44285d25c9e62869520cfa (patch) | |
| tree | fe528906c83ae14596080ca1231482227fbf7042 /tests/arch | |
| parent | ac2bb70b5287af66c7bc6b7ed532575c1955c75e (diff) | |
| download | yosys-f61f2a4078f36bbb1e44285d25c9e62869520cfa.tar.gz yosys-f61f2a4078f36bbb1e44285d25c9e62869520cfa.tar.bz2 yosys-f61f2a4078f36bbb1e44285d25c9e62869520cfa.zip | |
gowin: Fix LUT RAM inference, add more models.
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/gowin/lutram.ys | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/tests/arch/gowin/lutram.ys b/tests/arch/gowin/lutram.ys index 56f69e7c5..d668783a2 100644 --- a/tests/arch/gowin/lutram.ys +++ b/tests/arch/gowin/lutram.ys @@ -7,12 +7,11 @@ memory opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Called with -verify and proof did fail! -#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd lutram_1w1r -select -assert-count 8 t:RAM16S4 +select -assert-count 8 t:RAM16SDP4 # other logic present that is not simple #select -assert-none t:RAM16S4 %% t:* %D |