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* Tests for ram_style = "huge"KrystalDelusion2023-02-212-0/+37
| | | | iCE40 SPRAM and Xilinx URAM
* Reenable existing equiv_opt testsJannis Harder2022-10-071-1/+1
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* Fix tests for check in equiv_optJannis Harder2022-10-072-1/+3
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* support file locations containing spacesMiodrag Milanovic2022-08-081-0/+1
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* ice40: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-56/+0
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* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-111-27/+54
| | | | | | | | | | These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine.
* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-8/+8
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* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-0/+24
| | | | Fixes #2061.
* tests: Centralize test collection and Makefile generationXiretza2020-09-211-19/+3
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* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-301-1/+1
| | | | | | | | | The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* allow range for mux testMiodrag Milanovic2020-06-011-1/+2
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* test: ice40_dsp test to read +/ice40/cells_sim.v for default paramsEddie Hung2020-04-221-0/+1
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* tests: remove write_ilangEddie Hung2020-04-201-1/+0
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* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-102-15/+168
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-8/+28
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| * ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-061-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+6
| | | | | | | | LSE/Synplify use case insensitive matching.
| * ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-061-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * ice40: remove impossible test.whitequark2020-02-061-15/+0
| | | | | | | | | | | | iCE40 does not have LUTRAM. This was erroneously added in commit caab66111e2b5052bd26c8fd64b1324e7e4a4106, and tested for BRAM, essentially a duplicate of the "dpram.ys" test.
* | Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
|/ | | | line number.
* Import tests from #1628Eddie Hung2020-01-272-0/+102
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* ice40: reduce ABC9 internal fanout warnings with a param for CI->I3Eddie Hung2020-01-241-23/+4
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* Add #1644 testcaseEddie Hung2020-01-172-0/+2
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* ice40_dsp: add testEddie Hung2020-01-171-0/+11
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* Add #1626 testcaseEddie Hung2020-01-121-0/+217
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* Revert insertion of 'reg', leave note behindEddie Hung2020-01-011-1/+2
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* Fix warningsEddie Hung2019-12-312-2/+2
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* Call equiv_opt with -multiclock and -assertEddie Hung2019-12-311-1/+1
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* Add #1598 testcaseEddie Hung2019-12-271-0/+16
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* Rename memory tests to lutram, add more xilinx testsEddie Hung2019-12-121-3/+3
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* unmap $__ICE40_CARRY_WRAPPER in testEddie Hung2019-12-091-1/+21
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* ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-3/+5
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* Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-061-2/+2
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* Add WIP test for unwrapping $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+30
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* Check SB_CARRY name also preservedEddie Hung2019-12-031-0/+1
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* Add testcaseEddie Hung2019-12-031-0/+60
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* Fixed testsMiodrag Milanovic2019-11-111-5/+8
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* Common memory test now sharedMiodrag Milanovic2019-10-182-22/+1
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* Remove not needed testsMiodrag Milanovic2019-10-184-52/+0
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* Share common testsMiodrag Milanovic2019-10-1822-494/+127
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* Fix path to yosysMiodrag Milanovic2019-10-181-1/+1
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* Moved all tests in arch sub directoryMiodrag Milanovic2019-10-1838-0/+861
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