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| author | Jannis Harder <me@jix.one> | 2022-08-25 14:24:31 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-10-07 16:04:51 +0200 |
| commit | 81906aa627ed4a2d232a27a84e050bf86f2f83a6 (patch) | |
| tree | bb32810e3d7996f965a325fc1010c6ac414cfede /tests/arch/ice40 | |
| parent | 051630763741914c3ba3bdf25ea091395dbc00b4 (diff) | |
| download | yosys-81906aa627ed4a2d232a27a84e050bf86f2f83a6.tar.gz yosys-81906aa627ed4a2d232a27a84e050bf86f2f83a6.tar.bz2 yosys-81906aa627ed4a2d232a27a84e050bf86f2f83a6.zip | |
Fix tests for check in equiv_opt
Diffstat (limited to 'tests/arch/ice40')
| -rw-r--r-- | tests/arch/ice40/bug1597.ys | 3 | ||||
| -rw-r--r-- | tests/arch/ice40/ice40_opt.ys | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/tests/arch/ice40/bug1597.ys b/tests/arch/ice40/bug1597.ys index b7983cfa4..73bc18eb2 100644 --- a/tests/arch/ice40/bug1597.ys +++ b/tests/arch/ice40/bug1597.ys @@ -3,7 +3,7 @@ module top ( input CLK, PIN_1, PIN_2, PIN_3, PIN_4, PIN_5, PIN_6, PIN_7, PIN_8, PIN_9, PIN_10, PIN_11, PIN_12, PIN_13, PIN_25, output USBPU, PIN_14, PIN_15, PIN_16, PIN_17, PIN_18, - PIN_19, PIN_20, PIN_21, PIN_22, PIN_23, PIN_24, + PIN_19, ); assign USBPU = 0; @@ -67,6 +67,7 @@ module SSCounter6o (input wire rst, clk, adv, jmp, input wire [5:0] in, output w SB_LUT4 #(.LUT_INIT(16'h8BB8)) l5 (lo[5], in[5], jmp, out[5], co[4]); endmodule EOT +read_verilog -lib +/ice40/cells_sim.v hierarchy -top top flatten equiv_opt -multiclock -map +/ice40/cells_sim.v synth_ice40 diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys index 71b68431e..e779ab207 100644 --- a/tests/arch/ice40/ice40_opt.ys +++ b/tests/arch/ice40/ice40_opt.ys @@ -21,6 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O); endmodule EOT +read_verilog -icells -lib +/ice40/abc9_model.v +/ice40/cells_sim.v equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt design -load postopt select -assert-count 1 t:* |