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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-24 11:59:48 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-24 11:59:48 -0800 |
| commit | b1787615514f84c83c27d08011427e90c9bd0f4a (patch) | |
| tree | 9e9e7ac93681070e550c0cc19bd36da6f6729b71 /tests/arch/ice40 | |
| parent | da6abc014987ef562a577dc374bcb03aad9256cd (diff) | |
| download | yosys-b1787615514f84c83c27d08011427e90c9bd0f4a.tar.gz yosys-b1787615514f84c83c27d08011427e90c9bd0f4a.tar.bz2 yosys-b1787615514f84c83c27d08011427e90c9bd0f4a.zip | |
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
Diffstat (limited to 'tests/arch/ice40')
| -rw-r--r-- | tests/arch/ice40/ice40_opt.ys | 27 |
1 files changed, 4 insertions, 23 deletions
diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys index 5186d4800..011d98fef 100644 --- a/tests/arch/ice40/ice40_opt.ys +++ b/tests/arch/ice40/ice40_opt.ys @@ -1,24 +1,4 @@ read_verilog -icells -formal <<EOT -module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3); - parameter LUT = 0; - SB_CARRY carry ( - .I0(A), - .I1(B), - .CI(CI), - .CO(CO) - ); - \$lut #( - .WIDTH(4), - .LUT(LUT) - ) lut ( - .A({I0,A,B,I3}), - .Y(O) - ); -endmodule -EOT -design -stash unmap - -read_verilog -icells -formal <<EOT module top(input CI, I0, output [1:0] CO, output O); wire A = 1'b0, B = 1'b0; \$__ICE40_CARRY_WRAPPER #( @@ -26,13 +6,14 @@ module top(input CI, I0, output [1:0] CO, output O); // A[1]: 1100 1100 1100 1100 // A[2]: 1111 0000 1111 0000 // A[3]: 1111 1111 0000 0000 - .LUT(~16'b 0110_1001_1001_0110) + .LUT(~16'b 0110_1001_1001_0110), + .I3_IS_CI(1'b1) ) u0 ( .A(A), .B(B), .CI(CI), .I0(I0), - .I3(CI), + .I3(1'bx), .CO(CO[0]), .O(O) ); @@ -40,7 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O); endmodule EOT -equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt +equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt design -load postopt select -assert-count 1 t:* select -assert-count 1 t:$lut |