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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 18:39:32 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 18:39:32 -0800 |
| commit | c082329af33cd428f53f5afbcb51fab8de545090 (patch) | |
| tree | 1482aa45efeef28a4c6fdf969a2e3883ffc62a30 /tests/arch/ice40 | |
| parent | 22fe931c861aa3f557327baf9d12ec57006308d9 (diff) | |
| download | yosys-c082329af33cd428f53f5afbcb51fab8de545090.tar.gz yosys-c082329af33cd428f53f5afbcb51fab8de545090.tar.bz2 yosys-c082329af33cd428f53f5afbcb51fab8de545090.zip | |
Call equiv_opt with -multiclock and -assert
Diffstat (limited to 'tests/arch/ice40')
| -rw-r--r-- | tests/arch/ice40/counter.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys index f112eb97d..7bbc4f2c3 100644 --- a/tests/arch/ice40/counter.ys +++ b/tests/arch/ice40/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 6 t:SB_CARRY |