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| author | whitequark <whitequark@whitequark.org> | 2020-01-01 03:59:25 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-02-06 14:58:20 +0000 |
| commit | 29d130dee93c6c6c8dff51535e3a673065f3eb35 (patch) | |
| tree | 531308ef217420ffd57a0287f2e8bde6d7e3f1d3 /tests/arch/ice40 | |
| parent | d44848328b329489eda0719968c3f81d4d9a6b55 (diff) | |
| download | yosys-29d130dee93c6c6c8dff51535e3a673065f3eb35.tar.gz yosys-29d130dee93c6c6c8dff51535e3a673065f3eb35.tar.bz2 yosys-29d130dee93c6c6c8dff51535e3a673065f3eb35.zip | |
ice40: remove impossible test.
iCE40 does not have LUTRAM. This was erroneously added in commit
caab66111e2b5052bd26c8fd64b1324e7e4a4106, and tested for BRAM,
essentially a duplicate of the "dpram.ys" test.
Diffstat (limited to 'tests/arch/ice40')
| -rw-r--r-- | tests/arch/ice40/lutram.ys | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/tests/arch/ice40/lutram.ys b/tests/arch/ice40/lutram.ys deleted file mode 100644 index 1ba40f8ec..000000000 --- a/tests/arch/ice40/lutram.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog ../common/lutram.v -hierarchy -top lutram_1w1r -proc -memory -nomap -equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd lutram_1w1r -select -assert-count 1 t:SB_RAM40_4K -select -assert-none t:SB_RAM40_4K %% t:* %D |