aboutsummaryrefslogtreecommitdiffstats
path: root/tests/arch/ecp5
Commit message (Collapse)AuthorAgeFilesLines
* Genericising bug1836.ysKrystalDelusion2023-02-211-20/+12
|
* bug3205.ys removedKrystalDelusion2023-02-211-57/+0
| | | | Made redundant by TDP test(s) in memories.ys
* Testing TDP synth mappingKrystalDelusion2023-02-211-0/+10
| | | | | New common sync_ram_tdp. Used in ecp5 and gatemate mem*.ys.
* Addings tests for #1836 and #3205KrystalDelusion2023-02-213-0/+120
|
* ecp5: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-135/+18
|
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-0/+7
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-111-51/+102
| | | | | | | | | | These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine.
* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-17/+17
|
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-251-4/+4
| | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-9/+9
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-221-0/+24
| | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409.
* tests: Centralize test collection and Makefile generationXiretza2020-09-211-19/+3
|
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+3
|
* tests: tidy up testcaseEddie Hung2020-06-031-3/+0
|
* tests: add ecp5 latch testcase with -abc9Eddie Hung2020-05-251-0/+16
|
* tests: remove write_ilangEddie Hung2020-04-201-2/+0
|
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-101-0/+330
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-16/+62
| |
| * ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-061-0/+284
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* | Update bug1630.ys to use -lut 4 instead of lut fileEddie Hung2020-02-271-1/+1
|/
* Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-051-0/+32
|\
| * Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+32
| |
* | Update tests with reduced areaEddie Hung2020-01-211-3/+3
|/
* Add #1630 testcaseEddie Hung2020-01-132-0/+2
|
* Add testcase from #1459Eddie Hung2020-01-061-0/+25
|
* Do not do call equiv_opt when no sim model existsEddie Hung2019-12-312-4/+4
|
* Call equiv_opt with -multiclock and -assertEddie Hung2019-12-311-1/+1
|
* Merge pull request #1599 from YosysHQ/eddie/retry_1588Eddie Hung2019-12-301-0/+16
|\ | | | | Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
| * Add #1598 testcaseEddie Hung2019-12-271-0/+16
| |
* | Update resource countEddie Hung2019-12-281-3/+3
|/
* Rename memory tests to lutram, add more xilinx testsEddie Hung2019-12-121-3/+3
|
* Fixed testsMiodrag Milanovic2019-11-111-4/+9
|
* Common memory test now sharedMiodrag Milanovic2019-10-182-22/+1
|
* Share common testsMiodrag Milanovic2019-10-1822-302/+11
|
* Fix path to yosysMiodrag Milanovic2019-10-181-1/+1
|
* Moved all tests in arch sub directoryMiodrag Milanovic2019-10-1832-0/+668
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-17 03:08:18 +0000