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authorEddie Hung <eddie@fpgeh.com>2020-01-21 16:50:04 -0800
committerEddie Hung <eddie@fpgeh.com>2020-01-21 16:50:04 -0800
commit5aaa19f1ab33394accbe633cd96a3fbe281dd09a (patch)
treeb87b9e0ccd100d60553c3d30808ff4fc119113eb /tests/arch/ecp5
parent72e4540ca9749a0b7621e91e32e5aabf24b29b74 (diff)
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Update tests with reduced area
Diffstat (limited to 'tests/arch/ecp5')
-rw-r--r--tests/arch/ecp5/mux.ys6
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys
index 22866832d..92463aa32 100644
--- a/tests/arch/ecp5/mux.ys
+++ b/tests/arch/ecp5/mux.ys
@@ -39,8 +39,8 @@ proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 12 t:L6MUX21
-select -assert-count 34 t:LUT4
-select -assert-count 17 t:PFUMX
+select -assert-count 8 t:L6MUX21
+select -assert-count 26 t:LUT4
+select -assert-count 12 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D