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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-11-11 15:41:33 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-11-11 15:41:33 +0100 |
| commit | 3e0ffe05a79d3196b3644cddf422edb927673b04 (patch) | |
| tree | b518fa47c9a27aa37da0deceb66313d769e14c7c /tests/arch/ecp5 | |
| parent | 362f4f996d49cca4be240d5c96fba013dd56a8cb (diff) | |
| download | yosys-3e0ffe05a79d3196b3644cddf422edb927673b04.tar.gz yosys-3e0ffe05a79d3196b3644cddf422edb927673b04.tar.bz2 yosys-3e0ffe05a79d3196b3644cddf422edb927673b04.zip | |
Fixed tests
Diffstat (limited to 'tests/arch/ecp5')
| -rw-r--r-- | tests/arch/ecp5/fsm.ys | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/tests/arch/ecp5/fsm.ys b/tests/arch/ecp5/fsm.ys index f834a4c6b..ba91e5fc0 100644 --- a/tests/arch/ecp5/fsm.ys +++ b/tests/arch/ecp5/fsm.ys @@ -2,11 +2,16 @@ read_verilog ../common/fsm.v hierarchy -top fsm proc flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check + +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module + select -assert-count 1 t:L6MUX21 -select -assert-count 13 t:LUT4 -select -assert-count 5 t:PFUMX -select -assert-count 5 t:TRELLIS_FF +select -assert-count 15 t:LUT4 +select -assert-count 6 t:PFUMX +select -assert-count 6 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D |