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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-10-22 10:37:44 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-10-22 13:03:42 +0200 |
commit | eb76d35e8030f4befb596fee6d7682d39628dc69 (patch) | |
tree | 14fd7825e5eabf1e21b40c0d57b886596dbf54c6 /tests/arch/ecp5 | |
parent | 1a7a597e0720f66b59b896f8e7d537dee8e37744 (diff) | |
download | yosys-eb76d35e8030f4befb596fee6d7682d39628dc69.tar.gz yosys-eb76d35e8030f4befb596fee6d7682d39628dc69.tar.bz2 yosys-eb76d35e8030f4befb596fee6d7682d39628dc69.zip |
memory_dff: Fix needlessly duplicating enable bits.
When the register being merged into the EN signal happens to be a $sdff,
the current code creates a new $mux for every bit, even if they happen
to be identical (as is usually the case), preventing proper grouping
further down the flow. Fix this by adding a simple cache.
Fixes #2409.
Diffstat (limited to 'tests/arch/ecp5')
-rw-r--r-- | tests/arch/ecp5/bug2409.ys | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/tests/arch/ecp5/bug2409.ys b/tests/arch/ecp5/bug2409.ys new file mode 100644 index 000000000..5ba9cec17 --- /dev/null +++ b/tests/arch/ecp5/bug2409.ys @@ -0,0 +1,24 @@ +read_verilog <<EOT +module t (...); + +input CLK; +input [10:0] A; +input WE; +input C; +input [7:0] DI; +output reg [7:0] DO; + +reg [7:0] mem[2047:0]; + +always @(posedge CLK) begin + if (C) + if (WE) + mem[A] <= DI; + DO <= mem[A]; +end + +endmodule +EOT + +synth_ecp5 +select -assert-count 1 t:DP16KD |