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* Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
* Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
* Working for unsignedEddie Hung2019-07-181-52/+28
* CleanupEddie Hung2019-07-181-70/+58
* Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-181-31/+41
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| * mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
* | Make all operands signedEddie Hung2019-07-171-1/+1
* | Update commentEddie Hung2019-07-171-5/+3
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* Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
* A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
* Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
* SignednessEddie Hung2019-07-162-8/+8
* Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
* Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-164-27/+35
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| * xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| * xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 si...David Shah2019-07-162-4/+8
| * mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
| * mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
* | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
* | Do not swap if equalsEddie Hung2019-07-151-1/+1
* | Oops forgot these filesEddie Hung2019-07-152-0/+5
* | OUT port to Y in generic DSPEddie Hung2019-07-152-3/+3
* | Move DSP mapping back out to dsp_map.vEddie Hung2019-07-152-41/+40
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* Only swap if B_WIDTH > A_WIDTHEddie Hung2019-07-151-1/+1
* Tidy upEddie Hung2019-07-151-39/+26
* Move DSP48E1 model out of cells_xtra, initial multiply one in cells_simEddie Hung2019-07-152-82/+131
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1512-25/+609
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| * Merge pull request #1183 from whitequark/ice40-always-relutClifford Wolf2019-07-121-11/+5
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| | * synth_ice40: switch -relut to be always on.whitequark2019-07-111-10/+4
| | * synth_ice40: fix help text typo. NFC.whitequark2019-07-111-1/+1
| * | Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
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| | * | synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
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| * / xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv...Marcin Kościelnicki2019-07-112-6/+6
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* | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a littleEddie Hung2019-07-104-45/+42
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-105-102/+193
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| * Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-103-6/+15
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| | * Error out if -abc9 and -retime specifiedEddie Hung2019-07-103-6/+15
| * | Merge pull request #1148 from YosysHQ/xc7muxEddie Hung2019-07-106-49/+414
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| | * Add some spacingEddie Hung2019-07-101-9/+9
| | * Add some ASCII art explaining mux decompositionEddie Hung2019-07-101-0/+21
| | * Call muxpack and pmux2shiftx before cmp2lutEddie Hung2019-07-091-9/+12
| | * Restore opt_clean back to original placeEddie Hung2019-07-091-2/+1
| | * Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6Eddie Hung2019-07-091-0/+2
| | * Extend using A[1] to preserve don't careEddie Hung2019-07-091-1/+9
| | * Extend during mux decomposition with 1'bxEddie Hung2019-07-091-24/+3
| | * Fix typo and commentsEddie Hung2019-07-091-4/+4
| | * Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-092-19/+28
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| | * | synth_xilinx to call commands of synth -coarse directlyEddie Hung2019-07-091-3/+20
| | * | Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""Eddie Hung2019-07-091-2/+2
| | * | Fix spacingEddie Hung2019-07-091-1/+1
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