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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 14:38:13 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-10 14:38:13 -0700 |
| commit | bb2144ae733f1a2c5e629a8251bfbdcc15559aa4 (patch) | |
| tree | 2ba1b5b6cc0df7d6dba956905ca39fcc7b22ea75 /techlibs | |
| parent | 2f990a73192de15199c16c5c683228a97dc8ce2d (diff) | |
| parent | 6bbd286e033ed25bb49684316a86d6227dec4cd7 (diff) | |
| download | yosys-bb2144ae733f1a2c5e629a8251bfbdcc15559aa4.tar.gz yosys-bb2144ae733f1a2c5e629a8251bfbdcc15559aa4.tar.bz2 yosys-bb2144ae733f1a2c5e629a8251bfbdcc15559aa4.zip | |
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
Error out if -abc9 and -retime specified
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 3 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 5 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 13 |
3 files changed, 15 insertions, 6 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 3b0c2ea9e..9f409ca51 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -199,6 +199,9 @@ struct SynthEcp5Pass : public ScriptPass if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); + if (abc9 && retime) + log_cmd_error("-retime option not currently compatible with -abc9!\n"); + log_header(design, "Executing SYNTH_ECP5 pass.\n"); log_push(); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 9dd5d81f7..2c75215cb 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -227,6 +227,9 @@ struct SynthIce40Pass : public ScriptPass if (device_opt != "hx" && device_opt != "lp" && device_opt !="u") log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str()); + if (abc == "abc9" && retime) + log_cmd_error("-retime option not currently compatible with -abc9!\n"); + log_header(design, "Executing SYNTH_ICE40 pass.\n"); log_push(); @@ -296,7 +299,7 @@ struct SynthIce40Pass : public ScriptPass run("techmap"); else run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); - if ((retime || help_mode) && abc != "abc9") + if (retime || help_mode) run(abc + " -dff", "(only if -retime)"); run("ice40_opt"); } diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ef7660288..77daa745c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -26,8 +26,8 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate - // to one LUT6 (instead of a LUT5 + LUT2) +#define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate + // to one LUT6 (instead of a LUT5 + LUT2) struct SynthXilinxPass : public ScriptPass { @@ -207,7 +207,7 @@ struct SynthXilinxPass : public ScriptPass extra_args(args, argidx, design); if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s") - log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str()); + log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str()); if (widemux != 0 && widemux < 2) log_cmd_error("-widemux value must be 0 or >= 2.\n"); @@ -215,6 +215,9 @@ struct SynthXilinxPass : public ScriptPass if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); + if (abc9 && retime) + log_cmd_error("-retime option not currently compatible with -abc9!\n"); + log_header(design, "Executing SYNTH_XILINX pass.\n"); log_push(); @@ -370,9 +373,9 @@ struct SynthXilinxPass : public ScriptPass if (family != "xc7") log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n"); if (nowidelut) - run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : "")); + run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); else - run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : "")); + run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); } else { if (nowidelut) |