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* Add techlibs/xilinx/lut2lut.vClifford Wolf2017-07-102-0/+66
* Fix some c++ clang compiler errorsClifford Wolf2017-07-031-3/+3
* Apply minor coding style changes to coolrunner2 targetClifford Wolf2017-07-032-1/+1
* Merge pull request #352 from rqou/masterClifford Wolf2017-07-036-0/+645
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| * coolrunner2: Add a few more primitivesRobert Ou2017-06-251-0/+110
| * coolrunner2: Initial mapping of latchesRobert Ou2017-06-254-0/+63
| * coolrunner2: Initial mapping of DFFsRobert Ou2017-06-254-0/+76
| * coolrunner2: Remove redundant INVERT_PTCRobert Ou2017-06-252-4/+1
| * coolrunner2: Remove debug printsRobert Ou2017-06-251-2/+0
| * coolrunner2: Correctly handle $_NOT_ after $sopRobert Ou2017-06-251-5/+41
| * coolrunner2: Also construct the XOR cell in the macrocellRobert Ou2017-06-252-7/+34
| * coolrunner2: Initial techmapping for $sopRobert Ou2017-06-254-153/+268
| * coolrunner2: Initial commitRobert Ou2017-06-243-0/+223
* | greenpak4_counters: Changed generation of primitive names so that the absorbe...Andrew Zonenberg2017-06-241-3/+21
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* Add dff2ff.v techmap fileClifford Wolf2017-05-312-0/+15
* greenpak4_counters: Added support for parallel output from GP_COUNTx cellsAndrew Zonenberg2017-05-221-17/+70
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-0/+38
* Squelch trailing whitespaceLarry Doolittle2017-04-128-126/+126
* Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAsdh732017-04-058-0/+968
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2017-02-251-3/+4
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| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2017-02-141-2/+0
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| * \ Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2017-02-081-0/+8
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| * | | greenpak4: Added POUT to GP_COUNTx cellsAndrew Zonenberg2017-01-011-3/+4
* | | | Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-0/+16
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* | | Fix double-call of log_pop() in synth_greenpak4Clifford Wolf2017-02-141-2/+0
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* | Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+8
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* greenpak4: Added INT pin to GP_SPIAndrew Zonenberg2016-12-211-1/+3
* greenpak4: removed unused MISO pin from GP_SPIAndrew Zonenberg2016-12-211-1/+0
* greenpak4: Removed SPI_BUFFER parameterAndrew Zonenberg2016-12-201-1/+0
* greenpak4: replaced MOSI/MISO with single one-way SDAT pinAndrew Zonenberg2016-12-201-2/+1
* greenpak4: Changed port names on GP_SPI for clarityAndrew Zonenberg2016-12-201-4/+4
* greenpak4: Initial implementation of GP_SPI cellAndrew Zonenberg2016-12-201-0/+27
* greenpak4: Updated GP_DCMP cell modelAndrew Zonenberg2016-12-171-2/+20
* greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.Andrew Zonenberg2016-12-161-5/+10
* greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed inte...Andrew Zonenberg2016-12-151-5/+24
* greenpak4: More fixups of GP_DCMPx cellsAndrew Zonenberg2016-12-151-9/+3
* greenpak4: And another typo :(Andrew Zonenberg2016-12-151-1/+1
* greenpak4: Fixed another typoAndrew Zonenberg2016-12-151-1/+1
* greenpak4: Fixed typoAndrew Zonenberg2016-12-151-1/+1
* greenpak4: Cleaned up trailing spaces in cells_simAndrew Zonenberg2016-12-141-60/+60
* greenpak4: Added GP_DCMPREF / GP_DCMPMUXAndrew Zonenberg2016-12-141-0/+23
* Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUFAndrew Zonenberg2016-12-111-1/+9
* greenpak4: Added support for inferred input/output inverters on latchesAndrew Zonenberg2016-12-101-4/+17
* greenpak4: Can now techmap inferred D latches (without set/reset or output in...Andrew Zonenberg2016-12-103-0/+17
* greenpak4: Inverted D latch cells now have nQ instead of Q as output port nam...Andrew Zonenberg2016-12-101-15/+15
* Added GP_DLATCH and GP_DLATCHIAndrew Zonenberg2016-12-051-0/+18
* Initial implementation of techlib support for GreenPAK latches. Instantiation...Andrew Zonenberg2016-12-052-0/+120
* Updated help text for synth_greenpak4Andrew Zonenberg2016-12-051-0/+2
* Indenting fixes in gowin sim cell libClifford Wolf2016-11-081-20/+28
* Added hex constant support to write_verilogClifford Wolf2016-11-031-1/+1
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