aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Expand)AuthorAgeFilesLines
* Wrap LUTRAMs in order to capture comb/seq behaviourEddie Hung2019-08-205-36/+200
* Add LUTRAM delaysEddie Hung2019-08-201-3/+6
* Remove mapping rulesEddie Hung2019-08-201-33/+0
* Remove -icellsEddie Hung2019-08-201-2/+2
* Use abc_{map,unmap,model}.vEddie Hung2019-08-207-110/+324
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-203-6/+6
|\
| * Merge pull request #1304 from YosysHQ/eddie/abc9_refactorEddie Hung2019-08-203-19/+41
| |\
| | * Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-193-6/+6
* | | Add arrival times for SRL outputsEddie Hung2019-08-191-3/+5
* | | Add BRAM arrival timesEddie Hung2019-08-191-8/+10
* | | Add reference to source of Tclktoq timingEddie Hung2019-08-191-0/+2
* | | Add 'abc_arrival' attribute for flop outputsEddie Hung2019-08-191-6/+6
* | | Update box timingsEddie Hung2019-08-191-6/+9
* | | Move from cell attr to module attrEddie Hung2019-08-191-12/+6
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-197-165/+37
|\| |
| * | Merge branch 'master' into eddie/pr1266_againwhitequark2019-08-181-15/+5
| |\ \
| | * \ Merge pull request #1250 from bwidawsk/masterEddie Hung2019-08-161-15/+5
| | |\ \
| | | * | techlibs/intel: Clean up MakefileBen Widawsky2019-08-051-15/+5
| * | | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPEREddie Hung2019-08-121-1/+1
| * | | | Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...Eddie Hung2019-08-126-150/+32
| |/ / /
* | | | Use attributes instead of paramsEddie Hung2019-08-191-30/+12
* | | | Merge branch 'eddie/abc9_refactor' into xaig_dffEddie Hung2019-08-1641-297/+1397
|\ \ \ \ | | |_|/ | |/| |
| * | | Update abc_* attr in ecp5 and ice40Eddie Hung2019-08-162-11/+21
| * | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modulesEddie Hung2019-08-161-8/+20
| |/ /
| * | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-106-32/+150
| * | Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-105-20/+14
| |\ \
| | * | substr() -> compare()Eddie Hung2019-08-071-3/+3
| | * | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-1/+1
| | * | Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-117/+252
| | |\ \
| | * | | stoi -> atoiEddie Hung2019-08-073-3/+3
| | * | | Fix spacingEddie Hung2019-08-061-3/+3
| | * | | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-1/+1
| | * | | Make liberal use of IdString.in()Eddie Hung2019-08-061-14/+8
| * | | | Merge pull request #1270 from YosysHQ/eddie/alu_lcu_docClifford Wolf2019-08-101-8/+36
| |\ \ \ \
| | * | | | Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
| | * | | | A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
| | * | | | Add more commentsEddie Hung2019-08-091-4/+18
| | * | | | Add a few comments to document $alu and $lcuEddie Hung2019-08-081-9/+12
| | | |/ / | | |/| |
| * | | | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-2/+0
| * | | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-073-10/+17
| * | | | Add testEddie Hung2019-08-071-1/+10
| * | | | Remove ice40_unlutEddie Hung2019-08-072-107/+0
| * | | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-073-39/+14
| |/ / /
| * | | Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
| |\ \ \
| | * | | ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
| | |/ /
| * | | Merge pull request #1249 from mmicko/anlogic_fixClifford Wolf2019-08-071-16/+8
| |\ \ \ | | |/ / | |/| |
| | * | anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
| | |/
| * / Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+19
| |/
| * Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-023-6/+6
| |\
| | * Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-013-6/+6