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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 12:41:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 12:41:11 -0700 |
| commit | 5eda5fc7eb889b738739270f67349b1027951443 (patch) | |
| tree | bdb3ea2dda94bf226054ed88f90deede9aefff7a /techlibs | |
| parent | be9e4f1b674ef4fb3f02e99efcfda04ea27b2a68 (diff) | |
| download | yosys-5eda5fc7eb889b738739270f67349b1027951443.tar.gz yosys-5eda5fc7eb889b738739270f67349b1027951443.tar.bz2 yosys-5eda5fc7eb889b738739270f67349b1027951443.zip | |
Remove -icells
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 3525e4de9..d4874af45 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -230,9 +230,9 @@ struct SynthXilinxPass : public ScriptPass { if (check_label("begin")) { if (vpr) - run("read_verilog -lib -icells -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); + run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); else - run("read_verilog -lib -icells +/xilinx/cells_sim.v"); + run("read_verilog -lib +/xilinx/cells_sim.v"); run("read_verilog -lib +/xilinx/cells_xtra.v"); |