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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 16:40:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 16:40:24 -0700 |
| commit | 9776084eda50060594c6609295c7aa540bb400e1 (patch) | |
| tree | 5e2b503ebc6e5f12048be338e69ee2c0c8a81880 /techlibs | |
| parent | 9962e6fc1a13d37ce475be935b5d0987e9720094 (diff) | |
| download | yosys-9776084eda50060594c6609295c7aa540bb400e1.tar.gz yosys-9776084eda50060594c6609295c7aa540bb400e1.tar.bz2 yosys-9776084eda50060594c6609295c7aa540bb400e1.zip | |
Allow whitebox modules to be overwritten
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/tests/test_arith.ys | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys index 7e928ec78..ddb80b700 100644 --- a/techlibs/ice40/tests/test_arith.ys +++ b/techlibs/ice40/tests/test_arith.ys @@ -8,8 +8,6 @@ rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter -delete A:whitebox # Necessary since whiteboxes cannot - # be overwritten... synth_ice40 -top gate read_verilog test_arith.v |