Merge branch 'eddie/abc9_refactor' into xaig_dff

41 files changed, 1397 insertions, 297 deletions

diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc
index 34b1d4f8a..c4089dac2 100644
--- a/techlibs/anlogic/anlogic_determine_init.cc
+++ b/techlibs/anlogic/anlogic_determine_init.cc
@@ -50,7 +50,7 @@ struct AnlogicDetermineInitPass : public Pass {
 
 		extra_args(args, args.size(), design);
 
-		size_t cnt = 0;
+		int cnt = 0;
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct AnlogicDetermineInitPass : public Pass {
 				}
 			}
 		}
-		log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+		log_header(design, "Updated %d cells with determined init value.\n", cnt);
 	}
 } AnlogicDetermineInitPass;
 
diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc
index 741bf04cc..070d39a20 100644
--- a/techlibs/anlogic/anlogic_eqn.cc
+++ b/techlibs/anlogic/anlogic_eqn.cc
@@ -69,7 +69,7 @@ struct AnlogicEqnPass : public Pass {
 
 		extra_args(args, args.size(), design);
 
-		size_t cnt = 0;
+		int cnt = 0;
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
@@ -106,7 +106,7 @@ struct AnlogicEqnPass : public Pass {
 				}
 			}
 		}
-		log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt);
+		log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt);
 	}
 } AnlogicEqnPass;
 
diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v
index 11cd140ec..6d6a7ca37 100644
--- a/techlibs/anlogic/arith_map.v
+++ b/techlibs/anlogic/arith_map.v
@@ -42,10 +42,9 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
 	wire [Y_WIDTH-1:0] AA = A_buf;
 	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
 	wire [Y_WIDTH+1:0] COx;
-	wire [Y_WIDTH+1:0] C = {COx, CI};
+	wire [Y_WIDTH+2:0] C = {COx, CI};
 
     wire dummy;
-	(* keep *)
     AL_MAP_ADDER #(
     	.ALUTYPE("ADD_CARRY"))
     adder_cin  (
@@ -55,19 +54,6 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
-	  if(i==Y_WIDTH-1) begin
-	  		(* keep *)
-			AL_MAP_ADDER #(
-				.ALUTYPE("ADD"))
-			adder_cout  (
-				.c(C[Y_WIDTH]),
-				.o(COx[Y_WIDTH])
-			);				
-            assign CO = COx[Y_WIDTH];
-          end
-	  else
-	  begin
-	  	(* keep *)
 	    AL_MAP_ADDER #(
             .ALUTYPE("ADD")
         ) adder_i (
@@ -76,9 +62,15 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
             .c(C[i+1]),
             .o({COx[i+1],Y[i]})
         );
-		end		
 	  end: slice
 	endgenerate
 	/* End implementation */
+	AL_MAP_ADDER #(
+		.ALUTYPE("ADD"))
+	adder_cout  (
+		.c(C[Y_WIDTH+1]),
+		.o(COx[Y_WIDTH+1])
+	);				
+	assign CO = COx[Y_WIDTH+1];
 	assign X = AA ^ BB;
 endmodule
\ No newline at end of file
diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v
index 8aa1eb957..0d0757767 100644
--- a/techlibs/common/cmp2lut.v
+++ b/techlibs/common/cmp2lut.v
@@ -27,7 +27,7 @@ parameter _TECHMAP_CONSTVAL_A_ = 0;
 parameter _TECHMAP_CONSTMSK_B_ = 0;
 parameter _TECHMAP_CONSTVAL_B_ = 0;
 
-function automatic integer gen_lut;
+function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
 	input integer width;
 	input integer operation;
 	input integer swap;
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 289673e82..64720e598 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -230,6 +230,25 @@ endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
+//-     $_NMUX_ (A, B, S, Y)
+//-
+//- A 2-input inverting MUX gate.
+//-
+//- Truth table:    A B S | Y
+//-                -------+---
+//-                 0 - 0 | 1
+//-                 1 - 0 | 0
+//-                 - 0 1 | 1
+//-                 - 1 1 | 0
+//-
+module \$_NMUX_ (A, B, S, Y);
+input A, B, S;
+output Y;
+assign Y = S ? !B : !A;
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
 //-     $_MUX4_ (A, B, C, D, S, T, Y)
 //-
 //- A 4-input MUX gate.
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index a424d3089..7845a3fed 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -532,14 +532,26 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $lcu (P, G, CI, CO)
+//-
+//- Lookahead carry unit
+//- A building block dedicated to fast computation of carry-bits used in binary
+//- arithmetic operations. By replacing the ripple carry structure used in full-adder
+//- blocks, the more significant  bits of the sum can be expected to be computed more
+//- quickly.
+//- Typically created during `techmap` of $alu cells (see the "_90_alu" rule in
+//- +/techmap.v).
 module \$lcu (P, G, CI, CO);
 
 parameter WIDTH = 1;
 
-input [WIDTH-1:0] P, G;
-input CI;
+input [WIDTH-1:0] P;    // Propagate
+input [WIDTH-1:0] G;    // Generate
+input CI;               // Carry-in
 
-output reg [WIDTH-1:0] CO;
+output reg [WIDTH-1:0] CO; // Carry-out
 
 integer i;
 always @* begin
@@ -555,6 +567,17 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $alu (A, B, CI, BI, X, Y, CO)
+//-
+//- Arithmetic logic unit.
+//- A building block supporting both binary addition/subtraction operations, and
+//- indirectly, comparison operations.
+//- Typically created by the `alumacc` pass, which transforms:
+//-   $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
+//- cells into this $alu cell.
+//-
 module \$alu (A, B, CI, BI, X, Y, CO);
 
 parameter A_SIGNED = 0;
@@ -563,12 +586,16 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [A_WIDTH-1:0] A;
-input [B_WIDTH-1:0] B;
-output [Y_WIDTH-1:0] X, Y;
+input [A_WIDTH-1:0] A;      // Input operand
+input [B_WIDTH-1:0] B;      // Input operand
+output [Y_WIDTH-1:0] X;     // A xor B (sign-extended, optional B inversion,
+                            //          used in combination with
+                            //          reduction-AND for $eq/$ne ops)
+output [Y_WIDTH-1:0] Y;     // Sum
 
-input CI, BI;
-output [Y_WIDTH-1:0] CO;
+input CI;                   // Carry-in (set for $sub)
+input BI;                   // Invert-B (set for $sub)
+output [Y_WIDTH-1:0] CO;    // Carry-out
 
 wire [Y_WIDTH-1:0] AA, BB;
 
@@ -584,6 +611,7 @@ endgenerate
 wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};
 
 assign X = AA ^ BB;
+// Full adder
 assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};
 
 function get_carry;
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc
index 48da0d8ad..de0cbb29d 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cc
+++ b/techlibs/coolrunner2/coolrunner2_sop.cc
@@ -60,10 +60,8 @@ struct Coolrunner2SopPass : public Pass {
 			dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
-					cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
-					cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE" ||
-					cell->type == "\\LDCP" || cell->type == "\\LDCP_N")
+				if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
+							"\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
 				{
 					if (cell->hasPort("\\PRE"))
 						special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
@@ -257,10 +255,8 @@ struct Coolrunner2SopPass : public Pass {
 			pool<SigBit> sig_fed_by_ff;
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
-					cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
-					cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
-					cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
+				if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
+							"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
 				{
 					auto output = sigmap(cell->getPort("\\Q")[0]);
 					sig_fed_by_ff.insert(output);
@@ -270,13 +266,11 @@ struct Coolrunner2SopPass : public Pass {
 			// Look at all the FF inputs
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
-					cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
-					cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
-					cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
+				if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
+							"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
 				{
 					SigBit input;
-					if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
+					if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
 						input = sigmap(cell->getPort("\\T")[0]);
 					else
 						input = sigmap(cell->getPort("\\D")[0]);
@@ -300,7 +294,7 @@ struct Coolrunner2SopPass : public Pass {
 						xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
 						xor_cell->setPort("\\OUT", xor_to_ff_wire);
 
-						if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
+						if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
 							cell->setPort("\\T", xor_to_ff_wire);
 						else
 							cell->setPort("\\D", xor_to_ff_wire);
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index ff39ba4fe..73e18112f 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -4,8 +4,8 @@ OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index ca88d0a5b..864a3550f 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
-module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
-	           output S0, S1, COUT);
-
+(* abc_box_id=1, lib_whitebox *)
+module CCU2C(
+	(* abc_carry_in *) input CIN,
+	input  A0, B0, C0, D0, A1, B1, C1, D1,
+	output S0, S1,
+	(* abc_carry_out *) output COUT
+);
 	parameter [15:0] INIT0 = 16'h0000;
 	parameter [15:0] INIT1 = 16'h0000;
 	parameter INJECT1_0 = "YES";
@@ -104,12 +107,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
+//(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-	input [3:0] DI,
-	input [3:0] WAD,
-	input WRE, WCK,
-	input [3:0] RAD,
+	(* abc_scc_break *) input [3:0] DI,
+	(* abc_scc_break *) input [3:0] WAD,
+	(* abc_scc_break *) input       WRE,
+	input        WCK,
+	input  [3:0] RAD,
 	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
@@ -333,6 +337,31 @@ module TRELLIS_SLICE(
 	parameter [127:0] CCU2_INJECT1_0 = "NO";
 	parameter [127:0] CCU2_INJECT1_1 = "NO";
 	parameter WREMUX = "WRE";
+	parameter WCKMUX = "WCK";
+
+	parameter A0MUX = "A0";
+	parameter A1MUX = "A1";
+	parameter B0MUX = "B0";
+	parameter B1MUX = "B1";
+	parameter C0MUX = "C0";
+	parameter C1MUX = "C1";
+	parameter D0MUX = "D0";
+	parameter D1MUX = "D1";
+
+	wire A0m, B0m, C0m, D0m;
+	wire A1m, B1m, C1m, D1m;
+
+	generate
+		if (A0MUX == "1") assign A0m = 1'b1; else assign A0m = A0;
+		if (B0MUX == "1") assign B0m = 1'b1; else assign B0m = B0;
+		if (C0MUX == "1") assign C0m = 1'b1; else assign C0m = C0;
+		if (D0MUX == "1") assign D0m = 1'b1; else assign D0m = D0;
+		if (A1MUX == "1") assign A1m = 1'b1; else assign A1m = A1;
+		if (B1MUX == "1") assign B1m = 1'b1; else assign B1m = B1;
+		if (C1MUX == "1") assign C1m = 1'b1; else assign C1m = C1;
+		if (D1MUX == "1") assign D1m = 1'b1; else assign D1m = D1;
+
+	endgenerate
 
 	function [15:0] permute_initval;
 		input [15:0] initval;
@@ -350,13 +379,13 @@ module TRELLIS_SLICE(
 			LUT4 #(
 				.INIT(LUT0_INITVAL)
 			) lut4_0 (
-				.A(A0), .B(B0), .C(C0), .D(D0),
+				.A(A0m), .B(B0m), .C(C0m), .D(D0m),
 				.Z(F0)
 			);
 			LUT4 #(
 				.INIT(LUT1_INITVAL)
 			) lut4_1 (
-				.A(A1), .B(B1), .C(C1), .D(D1),
+				.A(A1m), .B(B1m), .C(C1m), .D(D1m),
 				.Z(F1)
 			);
 			// LUT expansion muxes
@@ -370,20 +399,20 @@ module TRELLIS_SLICE(
 				.INJECT1_1(CCU2_INJECT1_1)
 		  ) ccu2c_i (
 				.CIN(FCI),
-				.A0(A0), .B0(B0), .C0(C0), .D0(D0),
-				.A1(A1), .B1(B1), .C1(C1), .D1(D1),
+				.A0(A0m), .B0(B0m), .C0(C0m), .D0(D0m),
+				.A1(A1m), .B1(B1m), .C1(C1m), .D1(D1m),
 				.S0(F0), .S1(F1),
 				.COUT(FCO)
 			);
 		end else if (MODE == "RAMW") begin
-			assign WDO0 = C1;
-			assign WDO1 = A1;
-			assign WDO2 = D1;
-			assign WDO3 = B1;
-			assign WADO0 = D0;
-			assign WADO1 = B0;
-			assign WADO2 = C0;
-			assign WADO3 = A0;
+			assign WDO0 = C1m;
+			assign WDO1 = A1m;
+			assign WDO2 = D1m;
+			assign WDO3 = B1m;
+			assign WADO0 = D0m;
+			assign WADO1 = B0m;
+			assign WADO2 = C0m;
+			assign WADO3 = A0m;
 		end else if (MODE == "DPRAM") begin
 			TRELLIS_RAM16X2 #(
 				.INITVAL_0(permute_initval(LUT0_INITVAL)),
@@ -393,17 +422,19 @@ module TRELLIS_SLICE(
 				.DI0(WD0), .DI1(WD1),
 				.WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
 				.WRE(WRE), .WCK(WCK),
-				.RAD0(D0), .RAD1(B0), .RAD2(C0), .RAD3(A0),
+				.RAD0(D0m), .RAD1(B0m), .RAD2(C0m), .RAD3(A0m),
 				.DO0(F0), .DO1(F1)
 			);
 			// TODO: confirm RAD and INITVAL ordering
 			// DPRAM mode contract?
+`ifdef FORMAL
 			always @(*) begin
-				assert(A0==A1);
-				assert(B0==B1);
-				assert(C0==C1);
-				assert(D0==D1);
+				assert(A0m==A1m);
+				assert(B0m==B1m);
+				assert(C0m==C1m);
+				assert(D0m==D1m);
 			end
+`endif
 		end else begin
 			ERROR_UNKNOWN_SLICE_MODE error();
 		end
@@ -455,90 +486,206 @@ module DP16KD(
   input CSB2, CSB1, CSB0,
   output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
 );
-  parameter DATA_WIDTH_A = 18;
-  parameter DATA_WIDTH_B = 18;
-
-  parameter REGMODE_A = "NOREG";
-  parameter REGMODE_B = "NOREG";
-
-  parameter RESETMODE = "SYNC";
-  parameter ASYNC_RESET_RELEASE = "SYNC";
-
-  parameter CSDECODE_A = "0b000";
-  parameter CSDECODE_B = "0b000";
-
-  parameter WRITEMODE_A = "NORMAL";
-  parameter WRITEMODE_B = "NORMAL";
-
-  parameter CLKAMUX = "CLKA";
-  parameter CLKBMUX = "CLKB";
-
-  parameter GSR = "ENABLED";
-
-  parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter DATA_WIDTH_A = 18;
+	parameter DATA_WIDTH_B = 18;
+
+	parameter REGMODE_A = "NOREG";
+	parameter REGMODE_B = "NOREG";
+
+	parameter RESETMODE = "SYNC";
+	parameter ASYNC_RESET_RELEASE = "SYNC";
+
+	parameter CSDECODE_A = "0b000";
+	parameter CSDECODE_B = "0b000";
+
+	parameter WRITEMODE_A = "NORMAL";
+	parameter WRITEMODE_B = "NORMAL";
+
+	parameter DIA17MUX = "DIA17";
+	parameter DIA16MUX = "DIA16";
+	parameter DIA15MUX = "DIA15";
+	parameter DIA14MUX = "DIA14";
+	parameter DIA13MUX = "DIA13";
+	parameter DIA12MUX = "DIA12";
+	parameter DIA11MUX = "DIA11";
+	parameter DIA10MUX = "DIA10";
+	parameter DIA9MUX = "DIA9";
+	parameter DIA8MUX = "DIA8";
+	parameter DIA7MUX = "DIA7";
+	parameter DIA6MUX = "DIA6";
+	parameter DIA5MUX = "DIA5";
+	parameter DIA4MUX = "DIA4";
+	parameter DIA3MUX = "DIA3";
+	parameter DIA2MUX = "DIA2";
+	parameter DIA1MUX = "DIA1";
+	parameter DIA0MUX = "DIA0";
+	parameter ADA13MUX = "ADA13";
+	parameter ADA12MUX = "ADA12";
+	parameter ADA11MUX = "ADA11";
+	parameter ADA10MUX = "ADA10";
+	parameter ADA9MUX = "ADA9";
+	parameter ADA8MUX = "ADA8";
+	parameter ADA7MUX = "ADA7";
+	parameter ADA6MUX = "ADA6";
+	parameter ADA5MUX = "ADA5";
+	parameter ADA4MUX = "ADA4";
+	parameter ADA3MUX = "ADA3";
+	parameter ADA2MUX = "ADA2";
+	parameter ADA1MUX = "ADA1";
+	parameter ADA0MUX = "ADA0";
+	parameter CEAMUX = "CEA";
+	parameter OCEAMUX = "OCEA";
+	parameter CLKAMUX = "CLKA";
+	parameter WEAMUX = "WEA";
+	parameter RSTAMUX = "RSTA";
+	parameter CSA2MUX = "CSA2";
+	parameter CSA1MUX = "CSA1";
+	parameter CSA0MUX = "CSA0";
+	parameter DOA17MUX = "DOA17";
+	parameter DOA16MUX = "DOA16";
+	parameter DOA15MUX = "DOA15";
+	parameter DOA14MUX = "DOA14";
+	parameter DOA13MUX = "DOA13";
+	parameter DOA12MUX = "DOA12";
+	parameter DOA11MUX = "DOA11";
+	parameter DOA10MUX = "DOA10";
+	parameter DOA9MUX = "DOA9";
+	parameter DOA8MUX = "DOA8";
+	parameter DOA7MUX = "DOA7";
+	parameter DOA6MUX = "DOA6";
+	parameter DOA5MUX = "DOA5";
+	parameter DOA4MUX = "DOA4";
+	parameter DOA3MUX = "DOA3";
+	parameter DOA2MUX = "DOA2";
+	parameter DOA1MUX = "DOA1";
+	parameter DOA0MUX = "DOA0";
+	parameter DIB17MUX = "DIB17";
+	parameter DIB16MUX = "DIB16";
+	parameter DIB15MUX = "DIB15";
+	parameter DIB14MUX = "DIB14";
+	parameter DIB13MUX = "DIB13";
+	parameter DIB12MUX = "DIB12";
+	parameter DIB11MUX = "DIB11";
+	parameter DIB10MUX = "DIB10";
+	parameter DIB9MUX = "DIB9";
+	parameter DIB8MUX = "DIB8";
+	parameter DIB7MUX = "DIB7";
+	parameter DIB6MUX = "DIB6";
+	parameter DIB5MUX = "DIB5";
+	parameter DIB4MUX = "DIB4";
+	parameter DIB3MUX = "DIB3";
+	parameter DIB2MUX = "DIB2";
+	parameter DIB1MUX = "DIB1";
+	parameter DIB0MUX = "DIB0";
+	parameter ADB13MUX = "ADB13";
+	parameter ADB12MUX = "ADB12";
+	parameter ADB11MUX = "ADB11";
+	parameter ADB10MUX = "ADB10";
+	parameter ADB9MUX = "ADB9";
+	parameter ADB8MUX = "ADB8";
+	parameter ADB7MUX = "ADB7";
+	parameter ADB6MUX = "ADB6";
+	parameter ADB5MUX = "ADB5";
+	parameter ADB4MUX = "ADB4";
+	parameter ADB3MUX = "ADB3";
+	parameter ADB2MUX = "ADB2";
+	parameter ADB1MUX = "ADB1";
+	parameter ADB0MUX = "ADB0";
+	parameter CEBMUX = "CEB";
+	parameter OCEBMUX = "OCEB";
+	parameter CLKBMUX = "CLKB";
+	parameter WEBMUX = "WEB";
+	parameter RSTBMUX = "RSTB";
+	parameter CSB2MUX = "CSB2";
+	parameter CSB1MUX = "CSB1";
+	parameter CSB0MUX = "CSB0";
+	parameter DOB17MUX = "DOB17";
+	parameter DOB16MUX = "DOB16";
+	parameter DOB15MUX = "DOB15";
+	parameter DOB14MUX = "DOB14";
+	parameter DOB13MUX = "DOB13";
+	parameter DOB12MUX = "DOB12";
+	parameter DOB11MUX = "DOB11";
+	parameter DOB10MUX = "DOB10";
+	parameter DOB9MUX = "DOB9";
+	parameter DOB8MUX = "DOB8";
+	parameter DOB7MUX = "DOB7";
+	parameter DOB6MUX = "DOB6";
+	parameter DOB5MUX = "DOB5";
+	parameter DOB4MUX = "DOB4";
+	parameter DOB3MUX = "DOB3";
+	parameter DOB2MUX = "DOB2";
+	parameter DOB1MUX = "DOB1";
+	parameter DOB0MUX = "DOB0";
+
+	parameter WID = 0;
+
+	parameter GSR = "ENABLED";
+
+	parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 endmodule
 
 // TODO: Diamond flip-flops
diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/lutram.txt
index b94357429..b94357429 100644
--- a/techlibs/ecp5/dram.txt
+++ b/techlibs/ecp5/lutram.txt
diff --git a/techlibs/ecp5/drams_map.v b/techlibs/ecp5/lutrams_map.v
index 3b3de831f..3b3de831f 100644
--- a/techlibs/ecp5/drams_map.v
+++ b/techlibs/ecp5/lutrams_map.v
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 9f409ca51..143d1f95c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -71,10 +71,10 @@ struct SynthEcp5Pass : public ScriptPass
 		log("        do not use flipflops with CE in output netlist\n");
 		log("\n");
 		log("    -nobram\n");
-		log("        do not use BRAM cells in output netlist\n");
+		log("        do not use block RAM cells in output netlist\n");
 		log("\n");
-		log("    -nodram\n");
-		log("        do not use distributed RAM cells in output netlist\n");
+		log("    -nolutram\n");
+		log("        do not use LUT RAM cells in output netlist\n");
 		log("\n");
 		log("    -nowidelut\n");
 		log("        do not use PFU muxes to implement LUTs larger than LUT4s\n");
@@ -96,7 +96,7 @@ struct SynthEcp5Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, vpr;
+	bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, vpr;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -107,7 +107,7 @@ struct SynthEcp5Pass : public ScriptPass
 		noccu2 = false;
 		nodffe = false;
 		nobram = false;
-		nodram = false;
+		nolutram = false;
 		nowidelut = false;
 		flatten = true;
 		retime = false;
@@ -172,11 +172,11 @@ struct SynthEcp5Pass : public ScriptPass
 				nobram = true;
 				continue;
 			}
-			if (args[argidx] == "-nodram") {
-				nodram = true;
+			if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
+				nolutram = true;
 				continue;
 			}
-			if (args[argidx] == "-nowidelut" || args[argidx] == "-nomux") {
+			if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
 				nowidelut = true;
 				continue;
 			}
@@ -231,23 +231,27 @@ struct SynthEcp5Pass : public ScriptPass
 			run("synth -run coarse");
 		}
 
-		if (!nobram && check_label("bram", "(skip if -nobram)"))
+		if (!nobram && check_label("map_bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/ecp5/bram.txt");
 			run("techmap -map +/ecp5/brams_map.v");
 		}
 
-		if (!nodram && check_label("dram", "(skip if -nodram)"))
+		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
 		{
-			run("memory_bram -rules +/ecp5/dram.txt");
-			run("techmap -map +/ecp5/drams_map.v");
+			run("memory_bram -rules +/ecp5/lutram.txt");
+			run("techmap -map +/ecp5/lutrams_map.v");
 		}
 
-		if (check_label("fine"))
+		if (check_label("map_ffram"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
+		}
+
+		if (check_label("map_gates"))
+		{
 			if (noccu2)
 				run("techmap");
 			else
diff --git a/techlibs/gowin/determine_init.cc b/techlibs/gowin/determine_init.cc
index 991e5245a..d9a0880f6 100644
--- a/techlibs/gowin/determine_init.cc
+++ b/techlibs/gowin/determine_init.cc
@@ -50,7 +50,7 @@ struct DetermineInitPass : public Pass {
 
 		extra_args(args, args.size(), design);
 
-		size_t cnt = 0;
+		int cnt = 0;
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct DetermineInitPass : public Pass {
 				}
 			}
 		}
-		log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+		log_header(design, "Updated %d cells with determined init value.\n", cnt);
 	}
 } DetermineInitPass;
 
diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index f8e12b527..c0ea742e2 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: I0 I1 CI
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
+$__ICE40_FULL_ADDER 1 1 3 2
+400 379 316
 259 231 126
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index fbe4c56e6..d73b6d649 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: CI I0 I1
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
+$__ICE40_FULL_ADDER 1 1 3 2
+589 558 465
 675 609 186 
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-661 589 558 465
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index f44deabc4..42d666051 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: I0 I1 CI
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
-675 609 278
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-1285 1231 1205 874
+$__ICE40_FULL_ADDER 1 1 3 2
+1231 1205 874
+675  609  278
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 4449fdc1b..fe83a8e38 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,6 +44,15 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+`ifdef _ABC
+		\$__ICE40_FULL_ADDER carry (
+			.A(AA[i]),
+			.B(BB[i]),
+			.CI(C[i]),
+			.CO(CO[i]),
+			.O(Y[i])
+		);
+`else
 		SB_CARRY carry (
 			.I0(AA[i]),
 			.I1(BB[i]),
@@ -63,6 +72,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 			.I3(C[i]),
 			.O(Y[i])
 		);
+`endif
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 759549e30..b4b831165 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -61,3 +61,27 @@ module \$lut (A, Y);
   endgenerate
 endmodule
 `endif
+
+`ifdef _ABC
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
+  SB_CARRY carry (
+    .I0(A),
+    .I1(B),
+    .CI(CI),
+    .CO(CO)
+  );
+  SB_LUT4 #(
+    //         I0: 1010 1010 1010 1010
+    //         I1: 1100 1100 1100 1100
+    //         I2: 1111 0000 1111 0000
+    //         I3: 1111 1111 0000 0000
+    .LUT_INIT(16'b 0110_1001_1001_0110)
+  ) adder (
+    .I0(1'b0),
+    .I1(A),
+    .I2(B),
+    .I3(CI),
+    .O(O)
+  );
+endmodule
+`endif
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b746ba4e5..5b18fec27 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 2, lib_whitebox *)
+(* lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,11 +136,40 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+(* lib_whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
+(* abc_box_id = 1, lib_whitebox *)
+module \$__ICE40_FULL_ADDER (
+	(* abc_carry_out *) output CO,
+	output O,
+	input A,
+	input B,
+	(* abc_carry_in *) input CI
+);
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+	SB_LUT4 #(
+		//         I0: 1010 1010 1010 1010
+		//         I1: 1100 1100 1100 1100
+		//         I2: 1111 0000 1111 0000
+		//         I3: 1111 1111 0000 0000
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(CI),
+		.O(O)
+	);
+endmodule
+
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (output `SB_DFF_REG, input C, D);
@@ -1340,13 +1369,13 @@ module SB_MAC16 (
 	wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
 	wire [15:0] Ah, Al, Bh, Bl;
 	assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
-	assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
+	assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
 	assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
-	assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
-	assign p_Ah_Bh = Ah * Bh;
-	assign p_Al_Bh = Al * Bh;
-	assign p_Ah_Bl = Ah * Bl;
-	assign p_Al_Bl = Al * Bl;
+	assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
+	assign p_Ah_Bh = Ah * Bh; // F
+	assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J
+	assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K
+	assign p_Al_Bl = Al * Bl; // G
 
 	// Regs F and J
 	reg [15:0] rF, rJ;
@@ -1377,7 +1406,9 @@ module SB_MAC16 (
 	assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
 
 	// Adder Stage
-	assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
+	wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK};
+	wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ};
+	assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
 
 	// Reg H
 	reg [31:0] rH;
diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
index 4fa6b0792..1a139ffea 100644
--- a/techlibs/ice40/ice40_braminit.cc
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -69,13 +69,13 @@ static void run_ice40_braminit(Module *module)
 
 			for (int i = 0; i < GetSize(line); i++)
 			{
-				if (in_comment && line.substr(i, 2) == "*/") {
+				if (in_comment && line.compare(i, 2, "*/") == 0) {
 					line[i] = ' ';
 					line[i+1] = ' ';
 					in_comment = false;
 					continue;
 				}
-				if (!in_comment && line.substr(i, 2) == "/*")
+				if (!in_comment && line.compare(i, 2, "/*") == 0)
 					in_comment = true;
 				if (in_comment)
 					line[i] = ' ';
@@ -87,7 +87,7 @@ static void run_ice40_braminit(Module *module)
 				long value;
 
 				token = next_token(line, " \t\r\n");
-				if (token.empty() || token.substr(0, 2) == "//")
+				if (token.empty() || token.compare(0, 2, "//") == 0)
 					break;
 
 				if (token[0] == '@') {
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index f528607d6..d5106b805 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,6 +83,51 @@ static void run_ice40_opts(Module *module)
 			}
 			continue;
 		}
+
+		if (cell->type == "$__ICE40_FULL_ADDER")
+		{
+			SigSpec non_const_inputs, replacement_output;
+			int count_zeros = 0, count_ones = 0;
+
+			SigBit inbit[3] = {
+				cell->getPort("\\A"),
+				cell->getPort("\\B"),
+				cell->getPort("\\CI")
+			};
+			for (int i = 0; i < 3; i++)
+				if (inbit[i].wire == nullptr) {
+					if (inbit[i] == State::S1)
+						count_ones++;
+					else
+						count_zeros++;
+				} else
+					non_const_inputs.append(inbit[i]);
+
+			if (count_zeros >= 2)
+				replacement_output = State::S0;
+			else if (count_ones >= 2)
+				replacement_output = State::S1;
+			else if (GetSize(non_const_inputs) == 1)
+				replacement_output = non_const_inputs;
+
+			if (GetSize(replacement_output)) {
+				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+				module->connect(cell->getPort("\\CO")[0], replacement_output);
+				module->design->scratchpad_set_bool("opt.did_something", true);
+				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
+						log_id(module), log_id(cell), log_signal(replacement_output));
+				cell->type = "$lut";
+				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\Y", cell->getPort("\\O"));
+				cell->unsetPort("\\B");
+				cell->unsetPort("\\CI");
+				cell->unsetPort("\\CO");
+				cell->unsetPort("\\O");
+				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
+				cell->setParam("\\WIDTH", 4);
+			}
+			continue;
+		}
 	}
 
 	for (auto cell : sb_lut_cells)
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
index d16e6e6a3..f3f70ac1f 100644
--- a/techlibs/ice40/ice40_unlut.cc
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -56,10 +56,10 @@ static void run_ice40_unlut(Module *module)
 			cell->unsetParam("\\LUT_INIT");
 
 			cell->setPort("\\A", SigSpec({
-				get_bit_or_zero(cell->getPort("\\I3")),
-				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I0")),
 				get_bit_or_zero(cell->getPort("\\I1")),
-				get_bit_or_zero(cell->getPort("\\I0"))
+				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I3"))
 			}));
 			cell->setPort("\\Y", cell->getPort("\\O")[0]);
 			cell->unsetPort("\\I0");
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2c75215cb..dc04eed67 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -67,9 +67,6 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
-		log("    -relut\n");
-		log("        combine LUTs after synthesis\n");
-		log("\n");
 		log("    -nocarry\n");
 		log("        do not use SB_CARRY cells in output netlist\n");
 		log("\n");
@@ -78,7 +75,7 @@ struct SynthIce40Pass : public ScriptPass
 		log("\n");
 		log("    -dffe_min_ce_use <min_ce_use>\n");
 		log("        do not use SB_DFFE* cells if the resulting CE line would go to less\n");
-		log("        than min_ce_use SB_DFFE*in output netlist\n");
+		log("        than min_ce_use SB_DFFE* in output netlist\n");
 		log("\n");
 		log("    -nobram\n");
 		log("        do not use SB_RAM40_4K* cells in output netlist\n");
@@ -106,7 +103,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file, abc, device_opt;
-	bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
+	bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr;
 	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
@@ -122,7 +119,6 @@ struct SynthIce40Pass : public ScriptPass
 		dsp = false;
 		flatten = true;
 		retime = false;
-		relut = false;
 		noabc = false;
 		abc2 = false;
 		vpr = false;
@@ -175,7 +171,7 @@ struct SynthIce40Pass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-relut") {
-				relut = true;
+				// removed, opt_lut is always run
 				continue;
 			}
 			if (args[argidx] == "-nocarry") {
@@ -187,7 +183,7 @@ struct SynthIce40Pass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
-				min_ce_use = std::stoi(args[++argidx]);
+				min_ce_use = atoi(args[++argidx].c_str());
 				continue;
 			}
 			if (args[argidx] == "-nobram") {
@@ -242,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
+			run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -279,14 +275,14 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_clean");
 		}
 
-		if (!nobram && check_label("bram", "(skip if -nobram)"))
+		if (!nobram && check_label("map_bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/ice40/brams.txt");
 			run("techmap -map +/ice40/brams_map.v");
 			run("ice40_braminit");
 		}
 
-		if (check_label("map"))
+		if (check_label("map_ffram"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
@@ -298,7 +294,7 @@ struct SynthIce40Pass : public ScriptPass
 			if (nocarry)
 				run("techmap");
 			else
-				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
+				run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
 			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
@@ -342,15 +338,14 @@ struct SynthIce40Pass : public ScriptPass
 					else
 						wire_delay = 250;
 					run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+					run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
 				}
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
-			if (relut || help_mode) {
-				run("ice40_unlut", "                            (only if -relut)");
-				run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
-			}
+			run("ice40_unlut");
+			run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
 		}
 
 		if (check_label("map_cells"))
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
index 1bc0cc688..1e564d1b2 100644
--- a/techlibs/ice40/tests/test_dsp_model.sh
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -1,10 +1,15 @@
 #!/bin/bash
 set -ex
 sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
-cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
+if [ ! -f "test_dsp_model_ref.v" ]; then
+	cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
+fi
 for tb in testbench \
 		testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
-		testbench_seq_16x16_A testbench_seq_16x16_B
+		testbench_seq_16x16_A testbench_seq_16x16_B \
+		testbench_comb_8x8_A_signedA testbench_comb_8x8_A_signedB testbench_comb_8x8_A_signedAB \
+		testbench_comb_8x8_B_signedA testbench_comb_8x8_B_signedB testbench_comb_8x8_B_signedAB \
+		testbench_comb_16x16_signedA testbench_comb_16x16_signedB testbench_comb_16x16_signedAB
 do
 	iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
 	vvp -N ./test_dsp_model
diff --git a/techlibs/ice40/tests/test_dsp_model.v b/techlibs/ice40/tests/test_dsp_model.v
index 594bd4ad3..f4f6858f0 100644
--- a/techlibs/ice40/tests/test_dsp_model.v
+++ b/techlibs/ice40/tests/test_dsp_model.v
@@ -241,6 +241,81 @@ module testbench_comb_8x8_A;
 	) testbench ();
 endmodule
 
+module testbench_comb_8x8_A_signedA;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (2),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (0),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (2),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (0),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_A_signedB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (2),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (0),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (2),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (0),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_A_signedAB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (2),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (0),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (2),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (0),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
 module testbench_comb_8x8_B;
 	testbench #(
 		.NEG_TRIGGER               (0),
@@ -266,6 +341,81 @@ module testbench_comb_8x8_B;
 	) testbench ();
 endmodule
 
+module testbench_comb_8x8_B_signedA;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (1),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (1),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_B_signedB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (1),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (1),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_B_signedAB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (1),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (1),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
 module testbench_comb_16x16;
 	testbench #(
 		.NEG_TRIGGER               (0),
@@ -291,6 +441,81 @@ module testbench_comb_16x16;
 	) testbench ();
 endmodule
 
+module testbench_comb_16x16_signedA;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_16x16_signedB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
+module testbench_comb_16x16_signedAB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
 module testbench_seq_16x16_A;
 	testbench #(
 		.NEG_TRIGGER               (0),
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc
index ec7cea379..7a3d2c71a 100644
--- a/techlibs/intel/Makefile.inc
+++ b/techlibs/intel/Makefile.inc
@@ -3,8 +3,8 @@ OBJS += techlibs/intel/synth_intel.o
 
 $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
 $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
-$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams.txt))
-$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map.v))
+$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
+$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
 $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v))
 $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v))
 $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v))
diff --git a/techlibs/intel/common/brams.txt b/techlibs/intel/common/brams_m9k.txt
index 3bf21afc9..3bf21afc9 100644
--- a/techlibs/intel/common/brams.txt
+++ b/techlibs/intel/common/brams_m9k.txt
diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map_m9k.v
index d0f07c1de..d0f07c1de 100644
--- a/techlibs/intel/common/brams_map.v
+++ b/techlibs/intel/common/brams_map_m9k.v
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 09c9ba3af..e5dc1adc7 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -38,9 +38,9 @@ struct SynthIntelPass : public ScriptPass {
 		log("\n");
 		log("    -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
 		log("        generate the synthesis netlist for the specified family.\n");
-		log("        MAX10 is the default target if not family argument specified.\n");
+		log("        MAX10 is the default target if no family argument specified.\n");
 		log("        For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
-		log("        Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
+		log("        Cyclone V and Arria 10 GX devices are experimental.\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module (default='top')\n");
@@ -61,11 +61,11 @@ struct SynthIntelPass : public ScriptPass {
 		log("        from label is synonymous to 'begin', and empty to label is\n");
 		log("        synonymous to the end of the command list.\n");
 		log("\n");
-		log("    -noiopads\n");
-		log("        do not use altsyncram cells in output netlist\n");
+		log("    -iopads\n");
+		log("        use IO pad cells in output netlist\n");
 		log("\n");
 		log("    -nobram\n");
-		log("        do not use altsyncram cells in output netlist\n");
+		log("        do not use block RAM cells in output netlist\n");
 		log("\n");
 		log("    -noflatten\n");
 		log("        do not flatten design before synthesis\n");
@@ -79,7 +79,7 @@ struct SynthIntelPass : public ScriptPass {
 	}
 
 	string top_opt, family_opt, vout_file, blif_file;
-	bool retime, flatten, nobram, noiopads;
+	bool retime, flatten, nobram, iopads;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -90,7 +90,7 @@ struct SynthIntelPass : public ScriptPass {
 		retime = false;
 		flatten = true;
 		nobram = false;
-		noiopads = false;
+		iopads = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -125,8 +125,8 @@ struct SynthIntelPass : public ScriptPass {
 				run_to = args[argidx].substr(pos + 1);
 				continue;
 			}
-			if (args[argidx] == "-noiopads") {
-				noiopads = true;
+			if (args[argidx] == "-iopads") {
+				iopads = true;
 				continue;
 			}
 			if (args[argidx] == "-nobram") {
@@ -147,9 +147,13 @@ struct SynthIntelPass : public ScriptPass {
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
-		if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" &&
-		    family_opt != "cycloneive" && family_opt != "cyclone10")
-			log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
+		if (family_opt != "max10" &&
+		    family_opt != "a10gx" &&
+		    family_opt != "cyclonev" &&
+		    family_opt != "cycloneiv" &&
+		    family_opt != "cycloneive" &&
+		    family_opt != "cyclone10")
+			log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str());
 
 		log_header(design, "Executing SYNTH_INTEL pass.\n");
 		log_push();
@@ -162,18 +166,9 @@ struct SynthIntelPass : public ScriptPass {
 	void script() YS_OVERRIDE
 	{
 		if (check_label("begin")) {
-			if (check_label("family") && family_opt == "max10")
-				run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
-			else if (check_label("family") && family_opt == "a10gx")
-				run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
-			else if (check_label("family") && family_opt == "cyclonev")
-				run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
-			else if (check_label("family") && family_opt == "cyclone10")
-				run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
-			else if (check_label("family") && family_opt == "cycloneiv")
-				run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
-			else
-				run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
+			if (check_label("family"))
+				run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
+
 			// Misc and common cells
 			run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
 			run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
@@ -191,12 +186,19 @@ struct SynthIntelPass : public ScriptPass {
 			run("synth -run coarse");
 		}
 
-		if (!nobram && check_label("bram", "(skip if -nobram)")) {
-			run("memory_bram -rules +/intel/common/brams.txt");
-			run("techmap -map +/intel/common/brams_map.v");
+		if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
+                        if (family_opt == "cycloneiv" ||
+                            family_opt == "cycloneive" ||
+                            family_opt == "max10" ||
+                            help_mode) {
+				run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)");
+				run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)");
+			} else {
+				log_warning("BRAM mapping is not currently supported for %s.\n", family_opt.c_str());
+			}
 		}
 
-		if (check_label("fine")) {
+		if (check_label("map_ffram")) {
 			run("opt -fast -mux_undef -undriven -fine -full");
 			run("memory_map");
 			run("opt -undriven -fine");
@@ -220,20 +222,9 @@ struct SynthIntelPass : public ScriptPass {
 		}
 
 		if (check_label("map_cells")) {
-			if (!noiopads)
-				run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
-			if (family_opt == "max10")
-				run("techmap -map +/intel/max10/cells_map.v");
-			else if (family_opt == "a10gx")
-				run("techmap -map +/intel/a10gx/cells_map.v");
-			else if (family_opt == "cyclonev")
-				run("techmap -map +/intel/cyclonev/cells_map.v");
-			else if (family_opt == "cyclone10")
-				run("techmap -map +/intel/cyclone10/cells_map.v");
-			else if (family_opt == "cycloneiv")
-				run("techmap -map +/intel/cycloneiv/cells_map.v");
-			else
-				run("techmap -map +/intel/cycloneive/cells_map.v");
+			if (iopads || help_mode)
+				run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)");
+                        run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
 			run("dffinit -highlow -ff dffeas q power_up");
 			run("clean -purge");
 		}
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index c9a3a49fb..a9e0c5c7b 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -5,6 +5,8 @@ GENFILES += techlibs/xilinx/brams_init_36.vh
 GENFILES += techlibs/xilinx/brams_init_32.vh
 GENFILES += techlibs/xilinx/brams_init_18.vh
 GENFILES += techlibs/xilinx/brams_init_16.vh
+GENFILES += techlibs/xilinx/brams_init_9.vh
+GENFILES += techlibs/xilinx/brams_init_8.vh
 
 EXTRA_OBJS += techlibs/xilinx/brams_init.mk
 .SECONDARY: techlibs/xilinx/brams_init.mk
@@ -18,13 +20,18 @@ techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk
 techlibs/xilinx/brams_init_32.vh: techlibs/xilinx/brams_init.mk
 techlibs/xilinx/brams_init_18.vh: techlibs/xilinx/brams_init.mk
 techlibs/xilinx/brams_init_16.vh: techlibs/xilinx/brams_init.mk
+techlibs/xilinx/brams_init_9.vh: techlibs/xilinx/brams_init.mk
+techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk
 
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.txt))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
@@ -41,4 +48,6 @@ $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_18.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_16.vh))
+$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_9.vh))
+$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_8.vh))
 
diff --git a/techlibs/xilinx/brams_init.py b/techlibs/xilinx/brams_init.py
index d46a2b4f7..10057a0cb 100644
--- a/techlibs/xilinx/brams_init.py
+++ b/techlibs/xilinx/brams_init.py
@@ -1,5 +1,17 @@
 #!/usr/bin/env python3
 
+with open("techlibs/xilinx/brams_init_9.vh", "w") as f:
+    for i in range(4):
+        init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
+        for k in range(4, 256, 4):
+            init_snippets[k] = "\n           " + init_snippets[k]
+        print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
+    for i in range(32):
+        init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)]
+        for k in range(4, 32, 4):
+            init_snippets[k] = "\n          " + init_snippets[k]
+        print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
+
 with open("techlibs/xilinx/brams_init_18.vh", "w") as f:
     for i in range(8):
         init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
@@ -24,6 +36,10 @@ with open("techlibs/xilinx/brams_init_36.vh", "w") as f:
             init_snippets[k] = "\n          " + init_snippets[k]
         print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
 
+with open("techlibs/xilinx/brams_init_8.vh", "w") as f:
+    for i in range(32):
+        print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
+
 with open("techlibs/xilinx/brams_init_16.vh", "w") as f:
     for i in range(64):
         print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 2eb9fa2c1..b8e5bafc7 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -24,9 +24,9 @@ module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLA
 (* techmap_celltype = "$_DFF_PN0_" *)
 module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
 (* techmap_celltype = "$_DFF_NN1_" *)
-module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
 (* techmap_celltype = "$_DFF_PN1_" *)
-module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
 
 module \$__SHREG_ (input C, input D, input E, output Q);
   parameter DEPTH = 0;
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3937d3536..910d0e246 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -181,8 +181,14 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
-module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
+(* abc_box_id = 4, lib_whitebox *)
+module CARRY4(
+  (* abc_carry_out *) output [3:0] CO,
+  output [3:0] O,
+  (* abc_carry_in *) input CI,
+  input        CYINIT,
+  input  [3:0] DI, S
+);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
   assign CO[1] = S[1] ? CO[0] : DI[1];
@@ -226,7 +232,7 @@ module FDRE (output reg Q, input C, CE, D, R);
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
@@ -252,7 +258,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
@@ -289,10 +295,12 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc_box_id = 5, abc_scc_break="D,WE" *)
+(* abc_box_id = 5 *)
 module RAM32X1D (
   output DPO, SPO,
-  input  D, WCLK, WE,
+  (* abc_scc_break *) input D,
+  input  WCLK,
+  (* abc_scc_break *) input WE,
   input  A0, A1, A2, A3, A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
@@ -307,10 +315,12 @@ module RAM32X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 6, abc_scc_break="D,WE" *)
+(* abc_box_id = 6 *)
 module RAM64X1D (
   output DPO, SPO,
-  input  D, WCLK, WE,
+  (* abc_scc_break *) input D,
+  input  WCLK,
+  (* abc_scc_break *) input WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
@@ -325,10 +335,12 @@ module RAM64X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 7, abc_scc_break="D,WE" *)
+(* abc_box_id = 7 *)
 module RAM128X1D (
   output       DPO, SPO,
-  input        D, WCLK, WE,
+  (* abc_scc_break *) input D,
+  input        WCLK,
+  (* abc_scc_break *) input WE,
   input  [6:0] A, DPRA
 );
   parameter INIT = 128'h0;
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 13beaa6ae..4571f6d5c 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -33,10 +33,10 @@ module  \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPL
 module  \$_DFF_PN0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
 module  \$_DFF_PP0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
 
-module  \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
-module  \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
-module  \$_DFF_PP1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); FDPE   #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); FDPE   #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
 
 `endif
 
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d5ae124e0..6456dbdf4 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -195,7 +195,7 @@ struct SynthXilinxPass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
-				widemux = std::stoi(args[++argidx]);
+				widemux = atoi(args[++argidx].c_str());
 				continue;
 			}
 			if (args[argidx] == "-abc9") {
@@ -236,8 +236,13 @@ struct SynthXilinxPass : public ScriptPass
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");
 
-			if (!nobram || help_mode)
-				run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
+			if (help_mode) {
+				run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
+			} else if (family == "xc6s") {
+				run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
+			} else if (family == "xc7") {
+				run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
+			}
 
 			run(stringf("hierarchy -check %s", top_opt.c_str()));
 		}
@@ -280,9 +285,19 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("bram", "(skip if '-nobram')")) {
-			if (!nobram || help_mode) {
-				run("memory_bram -rules +/xilinx/brams.txt");
-				run("techmap -map +/xilinx/brams_map.v");
+			if (help_mode) {
+				run("memory_bram -rules +/xilinx/{family}_brams.txt");
+				run("techmap -map +/xilinx/{family}_brams_map.v");
+			} else if (!nobram) {
+				if (family == "xc6s") {
+					run("memory_bram -rules +/xilinx/xc6s_brams.txt");
+					run("techmap -map +/xilinx/xc6s_brams_map.v");
+				} else if (family == "xc7") {
+					run("memory_bram -rules +/xilinx/xc7_brams.txt");
+					run("techmap -map +/xilinx/xc7_brams_map.v");
+				} else {
+					log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
+				}
 			}
 		}
 
diff --git a/techlibs/xilinx/xc6s_brams.txt b/techlibs/xilinx/xc6s_brams.txt
new file mode 100644
index 000000000..17cd8e355
--- /dev/null
+++ b/techlibs/xilinx/xc6s_brams.txt
@@ -0,0 +1,84 @@
+
+bram $__XILINX_RAMB8BWER_SDP
+  init 1
+  abits 8
+  dbits 36
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 1 4
+  transp 0 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+bram $__XILINX_RAMB16BWER_TDP
+  init 1
+  abits  9     @a9d36
+  dbits 36     @a9d36
+  abits 10     @a10d18
+  dbits 18     @a10d18
+  abits 11     @a11d9
+  dbits  9     @a11d9
+  abits 12     @a12d4
+  dbits  4     @a12d4
+  abits 13     @a13d2
+  dbits  2     @a13d2
+  abits 14     @a14d1
+  dbits  1     @a14d1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 1 4   @a9d36
+  enable 1 2   @a10d18
+  enable 1 1   @a11d9 @a12d4 @a13d2 @a14d1
+  transp 0 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+bram $__XILINX_RAMB8BWER_TDP
+  init 1
+  abits  9     @a9d18
+  dbits 18     @a9d18
+  abits 10     @a10d9
+  dbits  9     @a10d9
+  abits 11     @a11d4
+  dbits  4     @a11d4
+  abits 12     @a12d2
+  dbits  2     @a12d2
+  abits 13     @a13d1
+  dbits  1     @a13d1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 1 2   @a9d18
+  enable 1 1   @a10d9 @a11d4 @a12d2 @a13d1
+  transp 0 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+match $__XILINX_RAMB8BWER_SDP
+  min bits 4096
+  min efficiency 5
+  shuffle_enable B
+  make_transp
+  or_next_if_better
+endmatch
+
+match $__XILINX_RAMB16BWER_TDP
+  min bits 4096
+  min efficiency 5
+  shuffle_enable B
+  make_transp
+  or_next_if_better
+endmatch
+
+match $__XILINX_RAMB8BWER_TDP
+  min bits 4096
+  min efficiency 5
+  shuffle_enable B
+  make_transp
+endmatch
+
diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v
new file mode 100644
index 000000000..eb1a29579
--- /dev/null
+++ b/techlibs/xilinx/xc6s_brams_bb.v
@@ -0,0 +1,211 @@
+module RAMB8BWER (
+	input CLKAWRCLK,
+	input CLKBRDCLK,
+	input ENAWREN,
+	input ENBRDEN,
+	input REGCEA,
+	input REGCEBREGCE,
+	input RSTA,
+	input RSTBRST,
+
+	input [12:0] ADDRAWRADDR,
+	input [12:0] ADDRBRDADDR,
+	input [15:0] DIADI,
+	input [15:0] DIBDI,
+	input [1:0] DIPADIP,
+	input [1:0] DIPBDIP,
+	input [1:0] WEAWEL,
+	input [1:0] WEBWEU,
+
+	output [15:0] DOADO,
+	output [15:0] DOBDO,
+	output [1:0] DOPADOP,
+	output [1:0] DOPBDOP
+);
+	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	parameter RAM_MODE = "TDP";
+	parameter integer DOA_REG = 0;
+	parameter integer DOB_REG = 0;
+
+	parameter integer DATA_WIDTH_A = 0;
+	parameter integer DATA_WIDTH_B = 0;
+
+	parameter WRITE_MODE_A = "WRITE_FIRST";
+	parameter WRITE_MODE_B = "WRITE_FIRST";
+
+	parameter EN_RSTRAM_A = "TRUE";
+	parameter EN_RSTRAM_B = "TRUE";
+
+	parameter INIT_A = 18'h000000000;
+	parameter INIT_B = 18'h000000000;
+	parameter SRVAL_A = 18'h000000000;
+	parameter SRVAL_B = 18'h000000000;
+
+	parameter RST_PRIORITY_A = "CE";
+	parameter RST_PRIORITY_B = "CE";
+
+	parameter RSTTYPE = "SYNC";
+
+	parameter SIM_COLLISION_CHECK = "ALL";
+endmodule
+
+module RAMB16BWER (
+	input CLKA,
+	input CLKB,
+	input ENA,
+	input ENB,
+	input REGCEA,
+	input REGCEB,
+	input RSTA,
+	input RSTB,
+
+	input [13:0] ADDRA,
+	input [13:0] ADDRB,
+	input [31:0] DIA,
+	input [31:0] DIB,
+	input [3:0] DIPA,
+	input [3:0] DIPB,
+	input [3:0] WEA,
+	input [3:0] WEB,
+
+	output [31:0] DOA,
+	output [31:0] DOB,
+	output [3:0] DOPA,
+	output [3:0] DOPB
+);
+	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	parameter integer DOA_REG = 0;
+	parameter integer DOB_REG = 0;
+
+	parameter integer DATA_WIDTH_A = 0;
+	parameter integer DATA_WIDTH_B = 0;
+
+	parameter WRITE_MODE_A = "WRITE_FIRST";
+	parameter WRITE_MODE_B = "WRITE_FIRST";
+
+	parameter EN_RSTRAM_A = "TRUE";
+	parameter EN_RSTRAM_B = "TRUE";
+
+	parameter INIT_A = 36'h000000000;
+	parameter INIT_B = 36'h000000000;
+	parameter SRVAL_A = 36'h000000000;
+	parameter SRVAL_B = 36'h000000000;
+
+	parameter RST_PRIORITY_A = "CE";
+	parameter RST_PRIORITY_B = "CE";
+
+	parameter RSTTYPE = "SYNC";
+
+	parameter SIM_COLLISION_CHECK = "ALL";
+endmodule
+
diff --git a/techlibs/xilinx/xc6s_brams_map.v b/techlibs/xilinx/xc6s_brams_map.v
new file mode 100644
index 000000000..16fd15e74
--- /dev/null
+++ b/techlibs/xilinx/xc6s_brams_map.v
@@ -0,0 +1,255 @@
+module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+	parameter [9215:0] INIT = 9216'bx;
+
+	input CLK2;
+	input CLK3;
+
+	input [7:0] A1ADDR;
+	output [35:0] A1DATA;
+	input A1EN;
+
+	input [7:0] B1ADDR;
+	input [35:0] B1DATA;
+	input [3:0] B1EN;
+
+	wire [12:0] A1ADDR_13 = {A1ADDR, 5'b0};
+	wire [12:0] B1ADDR_13 = {B1ADDR, 5'b0};
+
+	wire [3:0] DIP, DOP;
+	wire [31:0] DI, DO;
+
+	assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+	assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
+
+	RAMB8BWER #(
+		.RAM_MODE("SDP"),
+		.DATA_WIDTH_A(36),
+		.DATA_WIDTH_B(36),
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST"),
+		`include "brams_init_9.vh"
+	) _TECHMAP_REPLACE_ (
+		.DOBDO(DO[31:16]),
+		.DOADO(DO[15:0]),
+		.DOPBDOP(DOP[3:2]),
+		.DOPADOP(DOP[1:0]),
+		.DIBDI(DI[31:16]),
+		.DIADI(DI[15:0]),
+		.DIPBDIP(DIP[3:2]),
+		.DIPADIP(DIP[1:0]),
+		.WEBWEU(B1EN[3:2]),
+		.WEAWEL(B1EN[1:0]),
+
+		.ADDRAWRADDR(B1ADDR_13),
+		.CLKAWRCLK(CLK3 ^ !CLKPOL3),
+		.ENAWREN(|1),
+		.REGCEA(|0),
+		.RSTA(|0),
+
+		.ADDRBRDADDR(A1ADDR_13),
+		.CLKBRDCLK(CLK2 ^ !CLKPOL2),
+		.ENBRDEN(A1EN),
+		.REGCEBREGCE(|1),
+		.RSTBRST(|0)
+	);
+endmodule
+
+// ------------------------------------------------------------------------
+
+module \$__XILINX_RAMB16BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+	parameter CFG_ABITS = 9;
+	parameter CFG_DBITS = 36;
+	parameter CFG_ENABLE_B = 4;
+
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+	parameter [18431:0] INIT = 18432'bx;
+
+	input CLK2;
+	input CLK3;
+
+	input [CFG_ABITS-1:0] A1ADDR;
+	output [CFG_DBITS-1:0] A1DATA;
+	input A1EN;
+
+	input [CFG_ABITS-1:0] B1ADDR;
+	input [CFG_DBITS-1:0] B1DATA;
+	input [CFG_ENABLE_B-1:0] B1EN;
+
+	wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
+	wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
+	wire [3:0] B1EN_4 = {4{B1EN}};
+
+	wire [3:0] DIP, DOP;
+	wire [31:0] DI, DO;
+
+	wire [31:0] DOB;
+	wire [3:0] DOPB;
+
+	assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+	assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
+
+	generate if (CFG_DBITS > 8) begin
+		RAMB16BWER #(
+			.DATA_WIDTH_A(CFG_DBITS),
+			.DATA_WIDTH_B(CFG_DBITS),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
+			`include "brams_init_18.vh"
+		) _TECHMAP_REPLACE_ (
+			.DIA(32'd0),
+			.DIPA(4'd0),
+			.DOA(DO[31:0]),
+			.DOPA(DOP[3:0]),
+			.ADDRA(A1ADDR_14),
+			.CLKA(CLK2 ^ !CLKPOL2),
+			.ENA(A1EN),
+			.REGCEA(|1),
+			.RSTA(|0),
+			.WEA(4'b0),
+
+			.DIB(DI),
+			.DIPB(DIP),
+			.DOB(DOB),
+			.DOPB(DOPB),
+			.ADDRB(B1ADDR_14),
+			.CLKB(CLK3 ^ !CLKPOL3),
+			.ENB(|1),
+			.REGCEB(|0),
+			.RSTB(|0),
+			.WEB(B1EN_4)
+		);
+	end else begin
+		RAMB16BWER #(
+			.DATA_WIDTH_A(CFG_DBITS),
+			.DATA_WIDTH_B(CFG_DBITS),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
+			`include "brams_init_16.vh"
+		) _TECHMAP_REPLACE_ (
+			.DIA(32'd0),
+			.DIPA(4'd0),
+			.DOA(DO[31:0]),
+			.DOPA(DOP[3:0]),
+			.ADDRA(A1ADDR_14),
+			.CLKA(CLK2 ^ !CLKPOL2),
+			.ENA(A1EN),
+			.REGCEA(|1),
+			.RSTA(|0),
+			.WEA(4'b0),
+
+			.DIB(DI),
+			.DIPB(DIP),
+			.DOB(DOB),
+			.DOPB(DOPB),
+			.ADDRB(B1ADDR_14),
+			.CLKB(CLK3 ^ !CLKPOL3),
+			.ENB(|1),
+			.REGCEB(|0),
+			.RSTB(|0),
+			.WEB(B1EN_4)
+		);
+	end endgenerate
+endmodule
+
+// ------------------------------------------------------------------------
+
+module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+	parameter CFG_ABITS = 9;
+	parameter CFG_DBITS = 18;
+	parameter CFG_ENABLE_B = 2;
+
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+	parameter [9215:0] INIT = 9216'bx;
+
+	input CLK2;
+	input CLK3;
+
+	input [CFG_ABITS-1:0] A1ADDR;
+	output [CFG_DBITS-1:0] A1DATA;
+	input A1EN;
+
+	input [CFG_ABITS-1:0] B1ADDR;
+	input [CFG_DBITS-1:0] B1DATA;
+	input [CFG_ENABLE_B-1:0] B1EN;
+
+	wire [12:0] A1ADDR_13 = A1ADDR << (13 - CFG_ABITS);
+	wire [12:0] B1ADDR_13 = B1ADDR << (13 - CFG_ABITS);
+	wire [1:0] B1EN_2 = {2{B1EN}};
+
+	wire [1:0] DIP, DOP;
+	wire [15:0] DI, DO;
+
+	wire [15:0] DOBDO;
+	wire [1:0] DOPBDOP;
+
+	assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+	assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
+
+	generate if (CFG_DBITS > 8) begin
+		RAMB8BWER #(
+			.RAM_MODE("TDP"),
+			.DATA_WIDTH_A(CFG_DBITS),
+			.DATA_WIDTH_B(CFG_DBITS),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
+			`include "brams_init_9.vh"
+		) _TECHMAP_REPLACE_ (
+			.DIADI(16'b0),
+			.DIPADIP(2'b0),
+			.DOADO(DO),
+			.DOPADOP(DOP),
+			.ADDRAWRADDR(A1ADDR_13),
+			.CLKAWRCLK(CLK2 ^ !CLKPOL2),
+			.ENAWREN(A1EN),
+			.REGCEA(|1),
+			.RSTA(|0),
+			.WEAWEL(2'b0),
+
+			.DIBDI(DI),
+			.DIPBDIP(DIP),
+			.DOBDO(DOBDO),
+			.DOPBDOP(DOPBDOP),
+			.ADDRBRDADDR(B1ADDR_13),
+			.CLKBRDCLK(CLK3 ^ !CLKPOL3),
+			.ENBRDEN(|1),
+			.REGCEBREGCE(|0),
+			.RSTBRST(|0),
+			.WEBWEU(B1EN_2)
+		);
+	end else begin
+		RAMB8BWER #(
+			.RAM_MODE("TDP"),
+			.DATA_WIDTH_A(CFG_DBITS),
+			.DATA_WIDTH_B(CFG_DBITS),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
+			`include "brams_init_8.vh"
+		) _TECHMAP_REPLACE_ (
+			.DIADI(16'b0),
+			.DIPADIP(2'b0),
+			.DOADO(DO),
+			.DOPADOP(DOP),
+			.ADDRAWRADDR(A1ADDR_13),
+			.CLKAWRCLK(CLK2 ^ !CLKPOL2),
+			.ENAWREN(A1EN),
+			.REGCEA(|1),
+			.RSTA(|0),
+			.WEAWEL(2'b0),
+
+			.DIBDI(DI),
+			.DIPBDIP(DIP),
+			.DOBDO(DOBDO),
+			.DOPBDOP(DOPBDOP),
+			.ADDRBRDADDR(B1ADDR_13),
+			.CLKBRDCLK(CLK3 ^ !CLKPOL3),
+			.ENBRDEN(|1),
+			.REGCEBREGCE(|0),
+			.RSTBRST(|0),
+			.WEBWEU(B1EN_2)
+		);
+	end endgenerate
+endmodule
diff --git a/techlibs/xilinx/brams.txt b/techlibs/xilinx/xc7_brams.txt
index f1161114e..f1161114e 100644
--- a/techlibs/xilinx/brams.txt
+++ b/techlibs/xilinx/xc7_brams.txt
diff --git a/techlibs/xilinx/brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v
index a682ba4a7..a682ba4a7 100644
--- a/techlibs/xilinx/brams_bb.v
+++ b/techlibs/xilinx/xc7_brams_bb.v
diff --git a/techlibs/xilinx/brams_map.v b/techlibs/xilinx/xc7_brams_map.v
index 7ea49158d..7ea49158d 100644
--- a/techlibs/xilinx/brams_map.v
+++ b/techlibs/xilinx/xc7_brams_map.v