diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 12:19:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 12:19:25 -0700 |
| commit | 8a2480526f2ff80cbdf0f0f4279e8989b53b6e9b (patch) | |
| tree | d97d2d990b5823fe33590c8599d14ed638efec7a /techlibs | |
| parent | 12c692f6eda7367527fde2a8aad49447a73aa643 (diff) | |
| download | yosys-8a2480526f2ff80cbdf0f0f4279e8989b53b6e9b.tar.gz yosys-8a2480526f2ff80cbdf0f0f4279e8989b53b6e9b.tar.bz2 yosys-8a2480526f2ff80cbdf0f0f4279e8989b53b6e9b.zip | |
Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/cells_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index 0c10c9ac4..662423f0a 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -75,7 +75,7 @@ module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3); .WIDTH(4), .LUT(LUT) ) lut ( - .A({I3,B,A,I0}), + .A({I0,A,B,I3}), .Y(O) ); endmodule |