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* ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB modelgatecat2023-04-061-160/+30
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add more DFF typesMiodrag Milanovic2023-04-065-48/+102
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* Added proper simulation model for CCU2DMiodrag Milanovic2023-04-061-15/+35
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* Generate TRELLIS_DPR16X4 for lutramMiodrag Milanovic2023-04-063-21/+72
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* machxo2: Initial support for carry chains (CCU2D)Miodrag Milanovic2023-04-064-5/+127
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* Update Xilinx cell definitions, fixes #3699Miodrag Milanovic2023-03-233-6/+16
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* Start unification effort for machxo2 and ecp5Miodrag Milanovic2023-03-204-31/+23
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* Add additional iopad_external_pin attributesMiodrag Milanovic2023-03-201-4/+22
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* Add iopad_external_pin to some basic io primitivesMiodrag Milanovic2023-03-202-12/+13
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* insert IO buffers for ECP5, off by defaultMiodrag Milanovic2023-03-201-1/+14
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* ice40: Fix path delay definitionsStefan Riesenberger2023-03-101-14/+14
| | | | | | Parallel connections do not allow matching different bit widths. A full connection has to be used instead. Allows iverilog to parse the simulation library with hardware path delays enabled.
* Merge pull request #3688 from pu-cc/gatemate-reginitN. Engelhardt2023-03-013-8/+16
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| * gatemate: Enable register initializationPatrick Urban2023-02-153-8/+16
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* | Merge pull request #3663 from uis246/masterMiodrag Milanović2023-02-281-0/+17
|\ \ | | | | | | gowin: Add new types of oscillator
| * | gowin: Add new types of oscillatoruis2023-02-061-0/+17
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* | | Merge pull request #3652 from martell/elvdsMiodrag Milanović2023-02-281-0/+8
|\ \ \ | | | | | | | | gowin: Add support for emulated differential output
| * | | gowin: Add support for emulated differential outputmartell2023-01-291-0/+8
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* | | fabulous: Add support for mapping carry chainsgatecat2023-02-274-2/+93
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Check DREG attributeOliver Keszöcze2023-02-171-1/+1
| | | | | | | | | The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
* | | fabulous: Add CLK to BRAM interface primitivesgatecat2023-02-161-3/+3
| |/ |/| | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | gatemate: Update CC_PLL parametersPatrick Urban2023-02-141-0/+3
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* | gatemate: Add CC_USR_RSTN primitivePatrick Urban2023-02-141-0/+6
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* | gatemate: Ensure compatibility of LVDS ports with VHDLPatrick Urban2023-02-141-12/+12
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* Merge pull request #3630 from yrabbit/gw1n4c-pllMiodrag Milanović2023-01-181-0/+47
|\ | | | | gowin: add a new type of PLL - PLLVR
| * gowin: add a new type of PLL - PLLVRYRabbit2023-01-111-0/+47
| | | | | | | | | | | | | | This primitive is used in the GW1NS-4, GW1NS-4C, GW1NSR-4, GW1NSR-4C and GW1NSER-4C chips. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #3537 from jix/xpropJannis Harder2023-01-112-10/+60
|\ \ | |/ |/| New xprop pass
| * Add bitwise `$bweqx` and `$bwmux` cellsJannis Harder2022-11-302-1/+38
| | | | | | | | | | | | The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.
| * simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signalJannis Harder2022-11-301-2/+8
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| * simlib: Silence iverilog warning for `$lut`Jannis Harder2022-11-301-1/+1
| | | | | | | | | | | | iverilog complains about implicitly truncating LUT when connecting it to the `$bmux` A input. This explicitly truncates it to avoid that warning without changing the behaviour otherwise.
| * simlib: Fix wide $bmux and avoid iverilog warningsJannis Harder2022-11-301-2/+2
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| * satgen, simlib: Consistent x-propagation for `$pmux` cellsJannis Harder2022-11-301-4/+11
| | | | | | | | | | This updates satgen and simlib to use a `$pmux` model where the output is fully X when the S input is not all zero or one-hot with no x bits.
* | nexus: Fix BRAM write enable in PDP modegatecat2023-01-041-2/+2
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Allow adding extra custom prims and map rulesgatecat2022-11-171-0/+32
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: improvements to the passgatecat2022-11-176-139/+199
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Unify and update primitivesgatecat2022-11-173-852/+356
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Introduce RegFile mappingsTaoBi222022-11-174-2/+95
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* Replace synth call with components, reintroduce flags and correct vpr flag ↵TaoBi222022-11-171-4/+76
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* Reorder operations to load in primitive library before hierarchy passTaoBi222022-11-171-5/+6
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* Add plib flag to specify custom primitive library pathTaoBi222022-11-171-2/+14
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* Remove flattening from FABulous passTaoBi222022-11-171-11/+2
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* Remove ALL currently unused flags (some to be reintroduced later and passed ↵TaoBi222022-11-171-82/+3
| | | | through to synth)
* Add synth_fabulous ScriptPassTaoBi222022-11-178-0/+1282
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* simlib: Simplify recently changed $mux modelJannis Harder2022-10-281-4/+2
| | | | | | The use of a procedural continuous assignment introduced in #3526 was unintended and is completely unnecessary for the actual change of that PR.
* Merge pull request #3526 from jix/mux-simlib-evalJannis Harder2022-10-241-4/+1
|\ | | | | Consistent $mux undef handling
| * Consistent $mux undef handlingJannis Harder2022-10-241-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct.
* | Add smtmap.v describing the smt2 backend's behavior for undef bitsJannis Harder2022-10-202-0/+29
|/ | | | | | | | | Some builtin cells have an undefined (x) output even when all inputs are defined. This is not natively supported by the formal backends which will produce a fully defined value instead. This can lead to issues when combining different backends in a formal flow. To work around these, this adds a file containing verilog implementation of cells matching the fully defined behavior implemented by the smt2 backend.
* Test fixes for latest iverilogMiodrag Milanovic2022-09-212-3/+2
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* sf2: add NOTES about using yosys for smartfusion2 and igloo2Tristan Gingold2022-08-311-0/+84
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* sf2: add a test for $alu gateTristan Gingold2022-08-311-0/+22
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* sf2: suport $alu gate and ARI1 implementationTristan Gingold2022-08-312-2/+65
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