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| author | Jannis Harder <me@jix.one> | 2022-10-24 16:25:33 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-10-24 16:25:33 +0200 |
| commit | 408fc60c95f88671e0d6c5624a10e147334edb4e (patch) | |
| tree | b07daa89e730a8d8b76152d1b3a6174229452257 /techlibs | |
| parent | 3a37597e9f3cbcd69a28663933074c24d5c03feb (diff) | |
| parent | c77b7343d0412a009436a57764d907e2ae332da2 (diff) | |
| download | yosys-408fc60c95f88671e0d6c5624a10e147334edb4e.tar.gz yosys-408fc60c95f88671e0d6c5624a10e147334edb4e.tar.bz2 yosys-408fc60c95f88671e0d6c5624a10e147334edb4e.zip | |
Merge pull request #3526 from jix/mux-simlib-eval
Consistent $mux undef handling
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index ab9bd7e1d..2fd75372d 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1282,10 +1282,7 @@ input S; output reg [WIDTH-1:0] Y; always @* begin - if (S) - Y = B; - else - Y = A; + assign Y = S ? B : A; end endmodule |