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| author | gatecat <gatecat@ds0.me> | 2023-02-16 11:57:19 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-02-16 12:55:53 +0100 |
| commit | 25e7cb3bbb01d024b63cf8488cc3926f61e31804 (patch) | |
| tree | cab908b57938b7817d8781eb0718e7e8dc04b69c /techlibs | |
| parent | a20804c6ed0a734d13ddb43dda0f3ac976a62290 (diff) | |
| download | yosys-25e7cb3bbb01d024b63cf8488cc3926f61e31804.tar.gz yosys-25e7cb3bbb01d024b63cf8488cc3926f61e31804.tar.bz2 yosys-25e7cb3bbb01d024b63cf8488cc3926f61e31804.zip | |
fabulous: Add CLK to BRAM interface primitives
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/fabulous/prims.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/fabulous/prims.v b/techlibs/fabulous/prims.v index 8ddae5beb..bd0af906a 100644 --- a/techlibs/fabulous/prims.v +++ b/techlibs/fabulous/prims.v @@ -93,13 +93,13 @@ module Global_Clock (output CLK); endmodule (* blackbox, keep *) -module InPass4_frame_config (output O0, O1, O2, O3); +module InPass4_frame_config (input CLK, output O0, O1, O2, O3); endmodule (* blackbox, keep *) -module OutPass4_frame_config (input I0, I1, I2, I3); +module OutPass4_frame_config (input CLK, I0, I1, I2, I3); endmodule @@ -414,4 +414,4 @@ module LUTFF_ESS ( O <= D; end endmodule -`endif // COMPLEX_DFF
\ No newline at end of file +`endif // COMPLEX_DFF |