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| author | Jannis Harder <me@jix.one> | 2022-11-25 17:40:50 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-11-30 18:24:35 +0100 |
| commit | 99163fb822b08503fc99427d5368e24ab325b89b (patch) | |
| tree | 147a9e7d68977ffc723ec75708b5a1f61b5e80e3 /techlibs | |
| parent | 605d127517163f3d1113a6dbf19abcd55eb63dbb (diff) | |
| download | yosys-99163fb822b08503fc99427d5368e24ab325b89b.tar.gz yosys-99163fb822b08503fc99427d5368e24ab325b89b.tar.bz2 yosys-99163fb822b08503fc99427d5368e24ab325b89b.zip | |
simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index aca4d21a9..a22a3fd04 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1700,6 +1700,9 @@ endmodule // -------------------------------------------------------- `ifdef SIMLIB_FF +`ifndef SIMLIB_GLOBAL_CLOCK +`define SIMLIB_GLOBAL_CLOCK $global_clk +`endif module \$anyinit (D, Q); parameter WIDTH = 0; @@ -1709,7 +1712,7 @@ output reg [WIDTH-1:0] Q; initial Q <= 'bx; -always @($global_clk) begin +always @(`SIMLIB_GLOBAL_CLOCK) begin Q <= D; end @@ -1790,6 +1793,9 @@ endmodule `endif // -------------------------------------------------------- `ifdef SIMLIB_FF +`ifndef SIMLIB_GLOBAL_CLOCK +`define SIMLIB_GLOBAL_CLOCK $global_clk +`endif module \$ff (D, Q); @@ -1798,7 +1804,7 @@ parameter WIDTH = 0; input [WIDTH-1:0] D; output reg [WIDTH-1:0] Q; -always @($global_clk) begin +always @(`SIMLIB_GLOBAL_CLOCK) begin Q <= D; end |