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| author | N. Engelhardt <nak@yosyshq.com> | 2023-03-01 09:49:14 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-03-01 09:49:14 +0100 |
| commit | 1a3ff0d9267384dd8cd2ab4810fc561662f23b06 (patch) | |
| tree | 284172d33ca0645fcc21a77a9f5264574b873e16 /techlibs | |
| parent | bb28e48136fcd881090dca9b0c31429a91e6c1d4 (diff) | |
| parent | 2c7ba0e75225dff710fb7c5e87dd43bf881dcdd2 (diff) | |
| download | yosys-1a3ff0d9267384dd8cd2ab4810fc561662f23b06.tar.gz yosys-1a3ff0d9267384dd8cd2ab4810fc561662f23b06.tar.bz2 yosys-1a3ff0d9267384dd8cd2ab4810fc561662f23b06.zip | |
Merge pull request #3688 from pu-cc/gatemate-reginit
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/gatemate/cells_sim.v | 12 | ||||
| -rw-r--r-- | techlibs/gatemate/reg_map.v | 10 | ||||
| -rw-r--r-- | techlibs/gatemate/synth_gatemate.cc | 2 |
3 files changed, 16 insertions, 8 deletions
diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v index 7ed6d83ff..12e01d2df 100644 --- a/techlibs/gatemate/cells_sim.v +++ b/techlibs/gatemate/cells_sim.v @@ -242,7 +242,8 @@ module CC_DFF #( parameter [0:0] CLK_INV = 1'b0,
parameter [0:0] EN_INV = 1'b0,
parameter [0:0] SR_INV = 1'b0,
- parameter [0:0] SR_VAL = 1'b0
+ parameter [0:0] SR_VAL = 1'b0,
+ parameter [0:0] INIT = 1'bx
)(
input D,
(* clkbuf_sink *)
@@ -256,7 +257,7 @@ module CC_DFF #( assign en = (EN_INV) ? ~EN : EN;
assign sr = (SR_INV) ? ~SR : SR;
- initial Q = 1'bX;
+ initial Q = INIT;
always @(posedge clk or posedge sr)
begin
@@ -272,9 +273,10 @@ endmodule module CC_DLT #(
- parameter [0:0] G_INV = 1'b0,
+ parameter [0:0] G_INV = 1'b0,
parameter [0:0] SR_INV = 1'b0,
- parameter [0:0] SR_VAL = 1'b0
+ parameter [0:0] SR_VAL = 1'b0,
+ parameter [0:0] INIT = 1'bx
)(
input D,
input G,
@@ -285,7 +287,7 @@ module CC_DLT #( assign en = (G_INV) ? ~G : G;
assign sr = (SR_INV) ? ~SR : SR;
- initial Q = 1'bX;
+ initial Q = INIT;
always @(*)
begin
diff --git a/techlibs/gatemate/reg_map.v b/techlibs/gatemate/reg_map.v index 6a2c7fb91..6ec170a9d 100644 --- a/techlibs/gatemate/reg_map.v +++ b/techlibs/gatemate/reg_map.v @@ -21,25 +21,31 @@ module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DFF #(
.CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"),
.EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
- .SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1")
+ .SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1"),
+ .INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *)
module \$_DLATCH_xxx_ (input E, R, D, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DLT #(
.G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
- .SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1")
+ .SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1"),
+ .INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc index dd4fde643..1d46d7929 100644 --- a/techlibs/gatemate/synth_gatemate.cc +++ b/techlibs/gatemate/synth_gatemate.cc @@ -283,7 +283,7 @@ struct SynthGateMatePass : public ScriptPass if (check_label("map_regs"))
{
run("opt_clean");
- run("dfflegalize -cell $_DFFE_????_ x -cell $_DLATCH_???_ x");
+ run("dfflegalize -cell $_DFFE_????_ 01 -cell $_DLATCH_???_ 01");
run("techmap -map +/gatemate/reg_map.v");
run("opt_expr -mux_undef");
run("simplemap");
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