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| author | Jannis Harder <me@jix.one> | 2022-11-11 14:31:39 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-11-30 18:24:35 +0100 |
| commit | 39ac11340216eec2a040ace60feafd41f9cbb970 (patch) | |
| tree | 2cef8b73819f45c7f608d917c23c744549f75412 /techlibs | |
| parent | b982ab4f59298946021186403e6415ba79e59200 (diff) | |
| download | yosys-39ac11340216eec2a040ace60feafd41f9cbb970.tar.gz yosys-39ac11340216eec2a040ace60feafd41f9cbb970.tar.bz2 yosys-39ac11340216eec2a040ace60feafd41f9cbb970.zip | |
simlib: Fix wide $bmux and avoid iverilog warnings
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index b5e437d90..498cc27c2 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1300,11 +1300,11 @@ wire [WIDTH-1:0] bm0_out, bm1_out; generate if (S_WIDTH > 1) begin:muxlogic - \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A), .S(S[S_WIDTH-2:0]), .Y(bm0_out)); + \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out)); \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out)); assign Y = S[S_WIDTH-1] ? bm1_out : bm0_out; end else if (S_WIDTH == 1) begin:simple - assign Y = S ? A[1] : A[0]; + assign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0]; end else begin:passthru assign Y = A; end |