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| author | Patrick Urban <patrick.urban@colognechip.com> | 2023-02-14 07:51:31 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-02-14 12:02:41 +0100 |
| commit | 4cb27b1a3ac24cb6367533ac63cfc63123fab2de (patch) | |
| tree | 21d314e382eb25515d4f2f77db86cc78e077b21b /techlibs | |
| parent | e0bc25f1af26d6c152f72361f0fc10fc2c814357 (diff) | |
| download | yosys-4cb27b1a3ac24cb6367533ac63cfc63123fab2de.tar.gz yosys-4cb27b1a3ac24cb6367533ac63cfc63123fab2de.tar.bz2 yosys-4cb27b1a3ac24cb6367533ac63cfc63123fab2de.zip | |
gatemate: Ensure compatibility of LVDS ports with VHDL
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/gatemate/cells_sim.v | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v index 7e88fd7cf..7ed6d83ff 100644 --- a/techlibs/gatemate/cells_sim.v +++ b/techlibs/gatemate/cells_sim.v @@ -114,10 +114,10 @@ module CC_LVDS_IBUF #( parameter [0:0] FF_IBF = 1'bx
)(
(* iopad_external_pin *)
- input IP, IN,
+ input I_P, I_N,
output Y
);
- assign Y = IP;
+ assign Y = I_P;
endmodule
@@ -133,10 +133,10 @@ module CC_LVDS_OBUF #( )(
input A,
(* iopad_external_pin *)
- output OP, ON
+ output O_P, O_N
);
- assign OP = A;
- assign ON = ~A;
+ assign O_P = A;
+ assign O_N = ~A;
endmodule
@@ -152,10 +152,10 @@ module CC_LVDS_TOBUF #( )(
input A, T,
(* iopad_external_pin *)
- output OP, ON
+ output O_P, O_N
);
- assign OP = T ? 1'bz : A;
- assign ON = T ? 1'bz : ~A;
+ assign O_P = T ? 1'bz : A;
+ assign O_N = T ? 1'bz : ~A;
endmodule
@@ -174,12 +174,12 @@ module CC_LVDS_IOBUF #( )(
input A, T,
(* iopad_external_pin *)
- inout IOP, ION,
+ inout IO_P, IO_N,
output Y
);
- assign IOP = T ? 1'bz : A;
- assign ION = T ? 1'bz : ~A;
- assign Y = IOP;
+ assign IO_P = T ? 1'bz : A;
+ assign IO_N = T ? 1'bz : ~A;
+ assign Y = IO_P;
endmodule
|