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| author | Jannis Harder <me@jix.one> | 2022-11-10 16:31:45 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-11-30 18:24:35 +0100 |
| commit | 605d127517163f3d1113a6dbf19abcd55eb63dbb (patch) | |
| tree | 790e937d357143200a495c1ff8e3a3a1a6a57de1 /techlibs | |
| parent | 39ac11340216eec2a040ace60feafd41f9cbb970 (diff) | |
| download | yosys-605d127517163f3d1113a6dbf19abcd55eb63dbb.tar.gz yosys-605d127517163f3d1113a6dbf19abcd55eb63dbb.tar.bz2 yosys-605d127517163f3d1113a6dbf19abcd55eb63dbb.zip | |
simlib: Silence iverilog warning for `$lut`
iverilog complains about implicitly truncating LUT when connecting it to
the `$bmux` A input. This explicitly truncates it to avoid that warning
without changing the behaviour otherwise.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 498cc27c2..aca4d21a9 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1377,7 +1377,7 @@ parameter LUT = 0; input [WIDTH-1:0] A; output Y; -\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT), .S(A), .Y(Y)); +\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y)); endmodule |