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* sf2: add NOTES about using yosys for smartfusion2 and igloo2Tristan Gingold2022-08-311-0/+84
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* sf2: add a test for $alu gateTristan Gingold2022-08-311-0/+22
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* sf2: suport $alu gate and ARI1 implementationTristan Gingold2022-08-312-2/+65
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* synth_sf2: purge on last cleanTristan Gingold2022-08-311-2/+2
| | | | LiberoSoc don't like unused nets.
* sf2/cells_sim.v: add XTLOSC, SYSRESET cellsTristan Gingold2022-08-311-1/+110
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* sf2/cells_sim.v: add IOSTD parameter to I/O cellsTristan Gingold2022-08-311-0/+11
| | | | | This parameter is set by LiberoSoc IPs, so it is needed to avoid errors when using those IPs.
* synth_sf2: add -discard-ffinit option to discard ff initial valueTristan Gingold2022-08-311-1/+11
| | | | | | sf2 ff have no initial values, but some IP cores use initial values. In order to use those cores on sf2, it is required to discard the initial value (to be carefully used).
* Fitting help messages to 80 character widthKrystalDelusion2022-08-246-20/+25
| | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* Add the $anyinit cell and the formalff passJannis Harder2022-08-161-0/+17
| | | | | | | These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.
* Order ports with default assignments firstSean Anderson2022-08-091-10/+38
| | | | | | | | | | | | | | Although the current style is allowed by the standard, Icarus verilog doesn't parse default assignments using an implicit net type: techlibs/ice40/cells_sim.v:305: syntax error techlibs/ice40/cells_sim.v:1: Errors in port declarations. Fix this by making sure that ports with default assignments first on their line. Fixes: 46d3f03d2 ("Add default assignments to other SB_* simulation models") Signed-off-by: Sean Anderson <seanga2@gmail.com>
* nexus: Fix BRAM mapping.Marcelina Kościelnicka2022-08-091-18/+56
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* Merge pull request #3397 from pepijndevos/patch-2Miodrag Milanović2022-07-061-1/+0
|\ | | | | Apicula now supports lutram
| * Apicula now supports lutramPepijn de Vos2022-07-031-1/+0
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* | Fix static initialization, fixes mingw buildMiodrag Milanovic2022-07-041-20/+21
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* gatemate: Add LUT tree library scriptgatecat2022-06-276-6/+591
| | | | | Co-authored-by: Claire Xenia Wolf <claire@clairexen.net> Signed-off-by: gatecat <gatecat@ds0.me>
* gatemate: Add preliminary sim models for LUT tree structuresgatecat2022-06-271-0/+44
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.Marcelina Kościelnicka2022-06-024-7/+64
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* gatemate: Fix minor issues with `memory_libmap` (#3343)Patrick Urban2022-05-272-28/+39
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* gatemate: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-781/+927
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* machxo2: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-187-1/+578
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* efinix: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-90/+163
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* anlogic: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-303/+585
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* ice40: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-188-458/+293
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* xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-1837-2269/+4525
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* gowin: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-266/+576
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* nexus: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-1810-517/+677
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* ecp5: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-466/+584
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* Add missing parameters for ecp5Rick Luiken2022-04-252-1/+2
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* gowin: Add oscillator primitivesTim Pambor2022-03-281-0/+34
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* xilinx: Add RAMB4* blackboxesMarcelina Kościelnicka2022-03-212-1/+695
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* gowin: add support for Double Data Rate primitivesYRabbit2022-03-141-0/+25
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* intel_alm: M10K write-enable is negative-trueLofty2022-03-096-7/+28
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* gowin: Remove unnecessary attributesYRabbit2022-02-241-5/+0
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add support for true differential outputYRabbit2022-02-241-0/+11
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* ecp5: Do not use specify in generate in cells_sim.v.Marcelina Kościelnicka2022-02-211-28/+15
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* gowin: Add remaining block RAM blackboxes.Marcelina Kościelnicka2022-02-121-72/+527
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* gowin: Fix LUT RAM inference, add more models.Marcelina Kościelnicka2022-02-092-41/+241
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* ecp5: Fix DPR16X4 sim model.Marcelina Kościelnicka2022-02-091-1/+1
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* nexus: Fix arith_map CO signal.Marcelina Kościelnicka2022-02-061-1/+1
| | | | Fixes #3187.
* Fix the help message of synth_quicklogic.Xing GUO2022-01-311-2/+2
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* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-282-24/+87
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* nexus: Fix BB sim modelgatecat2022-01-191-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Removed dbits 8 since 9 will always be pickedMiodrag Milanovic2022-01-191-2/+0
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* Merge pull request #3120 from Icenowy/anlogic-bramMiodrag Milanović2022-01-196-1/+269
|\ | | | | anlogic: support BRAM mapping
| * anlogic: support BRAM mappingIcenowy Zheng2021-12-176-1/+269
| | | | | | | | | | | | | | | | | | | | | | Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | intel_alm: disable 256x40 M10K modeLofty2021-12-221-9/+3
|/ | | | | This BRAM mode uses both address ports, making it effectively single-port. Since memory_bram can't presently map to single-port memories, remove it.
* intel_alm: preliminary Arria V supportLofty2021-11-256-7/+199
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* synth_gatemate Revert cascade A/B port mixupPatrick Urban2021-11-132-12/+4
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* synth_gatemate: Remove iob_map invokationPatrick Urban2021-11-131-1/+0
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* synth_gatemate: Add block RAM cascade supportPatrick Urban2021-11-132-112/+96
| | | | | * add simulation model for block RAM cascade in 40K mode * limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
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