| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | | | Cleanup synth_xilinx | Eddie Hung | 2019-03-15 | 2 | -3/+2 | |
| | * | | | | | Working | Eddie Hung | 2019-03-15 | 2 | -47/+78 | |
| | * | | | | | Reverse bits in INIT parameter for Xilinx, since MSB is shifted first | Eddie Hung | 2019-03-14 | 1 | -16/+32 | |
| | * | | | | | Misspell | Eddie Hung | 2019-03-14 | 1 | -1/+1 | |
| | * | | | | | Revert "Add shregmap -init_msb_first and use in synth_xilinx" | Eddie Hung | 2019-03-14 | 1 | -3/+2 | |
| | * | | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-14 | 33 | -402/+1656 | |
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| | * | | | | | | Add shregmap -init_msb_first and use in synth_xilinx | Eddie Hung | 2019-03-14 | 1 | -2/+2 | |
| | * | | | | | | Fix cells_map for SRL | Eddie Hung | 2019-03-14 | 1 | -19/+17 | |
| | * | | | | | | Move shregmap until after first techmap | Eddie Hung | 2019-03-13 | 1 | -2/+2 | |
| | * | | | | | | Refactor $__SHREG__ in cells_map.v | Eddie Hung | 2019-03-13 | 1 | -32/+24 | |
| | * | | | | | | Remove SRL16/32 from cells_xtra | Eddie Hung | 2019-02-28 | 2 | -18/+2 | |
| | * | | | | | | Add SRL16 and SRL32 sim models | Eddie Hung | 2019-02-28 | 1 | -0/+39 | |
| | * | | | | | | Fix SRL16/32 techmap off-by-one | Eddie Hung | 2019-02-28 | 1 | -18/+24 | |
| | * | | | | | | synth_xilinx to call shregmap with enable support | Eddie Hung | 2019-02-28 | 2 | -24/+29 | |
| | * | | | | | | synth_xilinx to use shregmap with -params too | Eddie Hung | 2019-02-28 | 2 | -22/+19 | |
| | * | | | | | | synth_xilinx to now have shregmap call after dff2dffe | Eddie Hung | 2019-02-28 | 1 | -0/+2 | |
| | * | | | | | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 | Eddie Hung | 2019-02-28 | 1 | -0/+71 | |
| * | | | | | | | Add MUXCY and XORCY to cells_box.v | Eddie Hung | 2019-04-16 | 2 | -0/+15 | |
| * | | | | | | | Fix spacing | Eddie Hung | 2019-04-16 | 1 | -1/+1 | |
| * | | | | | | | Make cells.box whiteboxes not blackboxes | Eddie Hung | 2019-04-16 | 1 | -2/+2 | |
| * | | | | | | | read_verilog cells_box.v before techmap | Eddie Hung | 2019-04-16 | 1 | -1/+1 | |
| * | | | | | | | synth_xilinx: before abc read +/xilinx/cells_box.v | Eddie Hung | 2019-04-16 | 1 | -0/+1 | |
| * | | | | | | | Add +/xilinx/cells_box.v containing models for ABC boxes | Eddie Hung | 2019-04-16 | 2 | -0/+11 | |
| * | | | | | | | Revert "Add abc_box_id attribute to MUXF7/F8 cells" | Eddie Hung | 2019-04-16 | 1 | -2/+0 | |
| * | | | | | | | Add abc_box_id attribute to MUXF7/F8 cells | Eddie Hung | 2019-04-15 | 1 | -0/+2 | |
| * | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-15 | 3 | -41/+60 | |
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| | * | | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-12 | 1 | -1/+9 | |
| | * | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-12 | 4 | -44/+69 | |
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| | | * | | | | | Merge pull request #928 from litghost/add_xc7_sim_models | Eddie Hung | 2019-04-12 | 3 | -41/+60 | |
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| | | | * | | | | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 3 | -52/+14 | |
| | | | * | | | | | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 | |
| | | | * | | | | | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 | |
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| * | | | | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-04-12 | 1 | -3/+9 | |
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| | * | | | | | | Fixing issues in CycloneV cell sim | Diego | 2019-04-11 | 1 | -3/+9 | |
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| * | | | | | | Fix cells_map.v some more | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
| * | | | | | | More fine tuning | Eddie Hung | 2019-04-11 | 1 | -2/+2 | |
| * | | | | | | Fix cells_map.v | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
| * | | | | | | Fix typo | Eddie Hung | 2019-04-11 | 1 | -1/+1 | |
| * | | | | | | Juggle opt calls in synth_xilinx | Eddie Hung | 2019-04-11 | 2 | -30/+35 | |
| * | | | | | | WIP for cells_map.v -- maybe working? | Eddie Hung | 2019-04-10 | 1 | -32/+27 | |
| * | | | | | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 | Eddie Hung | 2019-04-10 | 1 | -31/+38 | |
| * | | | | | | Fix for when B_SIGNED = 1 | Eddie Hung | 2019-04-10 | 1 | -1/+8 | |
| * | | | | | | Update doc for synth_xilinx | Eddie Hung | 2019-04-10 | 1 | -7/+8 | |
| * | | | | | | ff_map.v after abc | Eddie Hung | 2019-04-10 | 1 | -5/+5 | |
| * | | | | | | Tidy up | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
| * | | | | | | Move map_cells to before map_luts | Eddie Hung | 2019-04-10 | 1 | -11/+12 | |
| * | | | | | | WIP for $shiftx to wide mux | Eddie Hung | 2019-04-10 | 1 | -1/+63 | |
| * | | | | | | Update LUT delays | Eddie Hung | 2019-04-10 | 1 | -11/+8 | |
| * | | | | | | Add cells.lut to techlibs/xilinx/ | Eddie Hung | 2019-04-09 | 2 | -0/+16 | |
| * | | | | | | synth_xilinx to call abc with -lut +/xilinx/cells.lut | Eddie Hung | 2019-04-09 | 1 | -2/+2 | |
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index : iCE40/yosys | |
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