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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 11:14:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 11:14:59 -0700 |
| commit | 8c6cf07acff290ab2132c1a7d262bf195fa85b8b (patch) | |
| tree | 85aca26a63d82d9d4addd369a508b4eddf052d64 /techlibs | |
| parent | 18108e024ae7d3b246aa83e8a9e7ac5327837d0a (diff) | |
| download | yosys-8c6cf07acff290ab2132c1a7d262bf195fa85b8b.tar.gz yosys-8c6cf07acff290ab2132c1a7d262bf195fa85b8b.tar.bz2 yosys-8c6cf07acff290ab2132c1a7d262bf195fa85b8b.zip | |
Revert "Add abc_box_id attribute to MUXF7/F8 cells"
This reverts commit 8fbbd9b129697152c93c35831c1d50982702a3ec.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 05dd9229f..0c8f282a4 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -159,12 +159,10 @@ module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule -(* abc_box_id = 1 *) module MUXF7(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule -(* abc_box_id = 2 *) module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule |