diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-10 08:49:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-10 08:49:39 -0700 |
| commit | 4dac9818bde02222f951c25ada5f3fd651ea4e36 (patch) | |
| tree | c20eedc2caa9205ce5e1afbff1ab67ed4d9a6d2c /techlibs | |
| parent | 3e368593eb22d16de60c44ea721ca146082d3472 (diff) | |
| download | yosys-4dac9818bde02222f951c25ada5f3fd651ea4e36.tar.gz yosys-4dac9818bde02222f951c25ada5f3fd651ea4e36.tar.bz2 yosys-4dac9818bde02222f951c25ada5f3fd651ea4e36.zip | |
Update LUT delays
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells.lut | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut index 3f3b69a8e..a1d9b9c42 100644 --- a/techlibs/xilinx/cells.lut +++ b/techlibs/xilinx/cells.lut @@ -1,15 +1,12 @@ # Max delays from https://pastebin.com/v2hrcksd # from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321 -# Since LUT delays are pushed onto the fabric as routing delays, -# assume each input costs +100ps - # K area delay -1 11 224 -2 12 224 324 -3 13 224 324 424 -4 14 224 324 424 524 -5 15 224 324 424 524 624 -6 20 224 324 424 524 624 724 -7 40 224 324 424 524 624 724 1020 -8 80 224 324 424 524 624 724 1020 1293 +1 11 624 +2 12 624 +3 13 624 +4 14 624 +5 15 624 +6 20 724 +7 40 1020 +8 80 1293 |