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| author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-04-09 11:43:19 -0700 |
|---|---|---|
| committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-04-09 11:43:19 -0700 |
| commit | e107ccdde82247e28c9c994240e4d4bf694f673f (patch) | |
| tree | a1ec0c984855a7b124baa5f17e18916ba1cfcc49 /techlibs | |
| parent | 5e0339855fc1f83b98694ed37dd2f195c3d8f52c (diff) | |
| download | yosys-e107ccdde82247e28c9c994240e4d4bf694f673f.tar.gz yosys-e107ccdde82247e28c9c994240e4d4bf694f673f.tar.bz2 yosys-e107ccdde82247e28c9c994240e4d4bf694f673f.zip | |
Fix LUT6_2 definition.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 315fd54c8..c96e0d8f1 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -149,9 +149,9 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5); assign O6 = I0 ? s1[1] : s1[0]; wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0]; - wire [ 7: 0] s5_3 = I3 ? s4[15: 8] : s4[ 7: 0]; - wire [ 3: 0] s5_2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s5_1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0]; + wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0]; + wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0]; assign O5 = I0 ? s5_1[1] : s5_1[0]; endmodule |