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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 12:41:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 12:41:56 -0700 |
| commit | 51896953626ddf7cffdbddfe64e8d85264d968a8 (patch) | |
| tree | 0f819f0560bd710ad708a861da908deafc8e1945 /techlibs | |
| parent | d259e6dc14dadf9101116c622569f5b961adde69 (diff) | |
| download | yosys-51896953626ddf7cffdbddfe64e8d85264d968a8.tar.gz yosys-51896953626ddf7cffdbddfe64e8d85264d968a8.tar.bz2 yosys-51896953626ddf7cffdbddfe64e8d85264d968a8.zip | |
read_verilog cells_box.v before techmap
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c10e42532..d5e9b80c8 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -282,8 +282,8 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { Pass::call(design, "opt -full"); - Pass::call(design, "techmap -map +/techmap.v"); Pass::call(design, "read_verilog +/xilinx/cells_box.v"); + Pass::call(design, "techmap -map +/techmap.v"); if (abc == "abc9") Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); else |