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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-10 08:50:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-10 08:50:31 -0700 |
| commit | 526aef9c2a9d61721add1c5ef1f85d439bfbb61e (patch) | |
| tree | 3b7765d128ac63ac4b36fe8c37b34a519d684001 /techlibs | |
| parent | e0b46eb4cbadafa5f03a5337f761d0ede2b993fa (diff) | |
| download | yosys-526aef9c2a9d61721add1c5ef1f85d439bfbb61e.tar.gz yosys-526aef9c2a9d61721add1c5ef1f85d439bfbb61e.tar.bz2 yosys-526aef9c2a9d61721add1c5ef1f85d439bfbb61e.zip | |
Move map_cells to before map_luts
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e2a2dfeeb..6d3999ae0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -264,33 +264,34 @@ struct SynthXilinxPass : public Pass Pass::call(design, "opt -full"); if (vpr) { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); + Pass::call(design, "techmap -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); } else { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); + Pass::call(design, "techmap -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); } Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); } + if (check_label(active, run_from, run_to, "map_cells")) + { + Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); + Pass::call(design, "clean"); + } + if (check_label(active, run_from, run_to, "map_luts")) { + Pass::call(design, "techmap -map +/techmap.v"); if (abc == "abc9") Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); else - Pass::call(design, abc + " -lut +/xilinx/cells.lut" + string(retime ? " -dff" : "")); + Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v"); } - if (check_label(active, run_from, run_to, "map_cells")) - { - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); - Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " - "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); - Pass::call(design, "clean"); - } - if (check_label(active, run_from, run_to, "check")) { Pass::call(design, "hierarchy -check"); |