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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 11:21:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 11:21:46 -0700 |
| commit | d259e6dc14dadf9101116c622569f5b961adde69 (patch) | |
| tree | 84145ab952d8b5cb26f91132648c8037f68d1755 /techlibs | |
| parent | 3ac4977b70a373cdabaa72e5f08050f49a3d4046 (diff) | |
| download | yosys-d259e6dc14dadf9101116c622569f5b961adde69.tar.gz yosys-d259e6dc14dadf9101116c622569f5b961adde69.tar.bz2 yosys-d259e6dc14dadf9101116c622569f5b961adde69.zip | |
synth_xilinx: before abc read +/xilinx/cells_box.v
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 0058f626f..c10e42532 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -283,6 +283,7 @@ struct SynthXilinxPass : public Pass { Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v"); + Pass::call(design, "read_verilog +/xilinx/cells_box.v"); if (abc == "abc9") Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); else |