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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-15 22:25:09 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-15 22:25:09 -0700 |
| commit | 8fbbd9b129697152c93c35831c1d50982702a3ec (patch) | |
| tree | 7a1e57662aff295f06a397d061a3f1feb8184d2a /techlibs | |
| parent | 538592067ec4d28bc11edd37bc19e472aae48c7b (diff) | |
| download | yosys-8fbbd9b129697152c93c35831c1d50982702a3ec.tar.gz yosys-8fbbd9b129697152c93c35831c1d50982702a3ec.tar.bz2 yosys-8fbbd9b129697152c93c35831c1d50982702a3ec.zip | |
Add abc_box_id attribute to MUXF7/F8 cells
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 0c8f282a4..05dd9229f 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -159,10 +159,12 @@ module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule +(* abc_box_id = 1 *) module MUXF7(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule +(* abc_box_id = 2 *) module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule |