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* Added greenpak4_dffinvClifford Wolf2016-08-153-0/+199
* greenpak4: Changed name of inverted output ports for consistencyAndrew Zonenberg2016-08-142-19/+19
* greenpak4: Added GP_DFFxI cellsAndrew Zonenberg2016-08-142-0/+68
* greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)Andrew Zonenberg2016-08-131-10/+10
* synth_greenpak4: use attrmvcp to move LOC from wires to cells.whitequark2016-08-101-0/+2
* Added GP_DAC cellAndrew Zonenberg2016-07-111-0/+8
* Removed VOUT port of GP_BANDGAPAndrew Zonenberg2016-07-111-1/+1
* Removed splitnets in prep for new gp4par parserAndrew Zonenberg2016-07-111-1/+0
* greenpak4: add GP_COUNT{8,14}_ADV cells.whitequark2016-07-101-0/+26
* Added "nlutmap -assert"Clifford Wolf2016-06-091-3/+3
* Added GP_DELAY cellAndrew Zonenberg2016-05-071-0/+29
* Fixed typo in port nameAndrew Zonenberg2016-05-071-1/+1
* Fixed extra semicolonAndrew Zonenberg2016-05-071-1/+1
* Fixed typo in parameter nameAndrew Zonenberg2016-05-071-1/+1
* Added simulation timescale declarationAndrew Zonenberg2016-05-071-0/+2
* Changed order of passes for better handling of INIT attributes on "output reg...Andrew Zonenberg2016-05-041-2/+2
* Renamed module parameterAndrew Zonenberg2016-05-041-4/+4
* Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cell...Andrew Zonenberg2016-05-043-18/+1
* Fixed incorrect signal naming in GP_IOBUFAndrew Zonenberg2016-05-041-2/+2
* Added tri-state I/O extraction for GreenPakAndrew Zonenberg2016-05-035-2/+29
* Added GreenPak I/O buffer cellsAndrew Zonenberg2016-05-031-0/+17
* Added comment to clarify GP_ABUF cellAndrew Zonenberg2016-05-021-0/+2
* Added GP_ABUF cellAndrew Zonenberg2016-05-021-0/+6
* Added GP_PGA cellAndrew Zonenberg2016-04-271-0/+11
* Removed VIN_BUF_ENAndrew Zonenberg2016-04-241-1/+0
* Renamed VOUT to OUT on GP_ACMP cellAndrew Zonenberg2016-04-231-1/+3
* Added GP_ACMP cellAndrew Zonenberg2016-04-231-0/+12
* Run clean after splitnets in synth_greenpak4Clifford Wolf2016-04-231-1/+1
* Merge https://github.com/azonenberg/yosysClifford Wolf2016-04-231-1/+7
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| * Fixed typoAndrew Zonenberg2016-04-221-1/+1
| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-222-2/+2
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| * | Added GP_VREF cellAndrew Zonenberg2016-04-201-0/+6
* | | Added "shregmap" to synth_greenpak4Clifford Wolf2016-04-231-0/+1
* | | Converted synth_greenpak4 to ScriptPassClifford Wolf2016-04-231-108/+69
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* | Added "yosys -D" featureClifford Wolf2016-04-212-2/+2
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* Added GP_SHREG cellAndrew Zonenberg2016-04-131-0/+23
* Refactoring: alphabetized cells_simAndrew Zonenberg2016-04-131-120/+119
* Fixed missing semicolonAndrew Zonenberg2016-04-091-1/+1
* Added GP_RCOSC cellAndrew Zonenberg2016-04-091-0/+38
* Fixed assertion failure for non-inferrable counters in some casesAndrew Zonenberg2016-04-061-2/+6
* Added second divider to GP_RINGOSCAndrew Zonenberg2016-04-061-8/+13
* Added GP_RINGOSC primitiveAndrew Zonenberg2016-04-061-0/+26
* Added GP_PORAndrew Zonenberg2016-04-041-0/+22
* Added GP_BANDGAP cellAndrew Zonenberg2016-04-041-0/+9
* Removed more debug printsAndrew Zonenberg2016-04-011-1/+0
* Removed forgotten debug codeAndrew Zonenberg2016-04-011-7/+1
* Added GreenPak inverter supportAndrew Zonenberg2016-04-013-4/+13
* Added support for inferring counters with asynchronous resets. Fixed use-afte...Andrew Zonenberg2016-04-011-51/+210
* DFFINIT is now correctly called for all kinds of flipflop, not just DFFAndrew Zonenberg2016-03-311-0/+6
* Fixed incorrect port name in cells_map.vAndrew Zonenberg2016-03-311-2/+2
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