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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-20 20:48:19 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-20 20:48:19 -0700 |
| commit | d90c1e952256dc00d070863835e061d73e4bc6b3 (patch) | |
| tree | 910d671291246d476f0b1ff9e7258cce6840f89b /techlibs/greenpak4 | |
| parent | bf64974d43600b2e8ad63a1762489a152c002a41 (diff) | |
| download | yosys-d90c1e952256dc00d070863835e061d73e4bc6b3.tar.gz yosys-d90c1e952256dc00d070863835e061d73e4bc6b3.tar.bz2 yosys-d90c1e952256dc00d070863835e061d73e4bc6b3.zip | |
Added GP_VREF cell
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 554e2e13f..40d79aeae 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -263,6 +263,12 @@ module GP_VDD(output OUT); assign OUT = 1; endmodule +module GP_VREF(input VIN, output reg VOUT); + parameter VIN_DIV = 1; + parameter VREF = 0; + //cannot simulate mixed signal IP +endmodule + module GP_VSS(output OUT); assign OUT = 0; endmodule |