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authorAndrew Zonenberg <azonenberg@drawersteak.com>2016-04-09 01:17:13 -0700
committerAndrew Zonenberg <azonenberg@drawersteak.com>2016-04-09 01:17:13 -0700
commit58d87156815871c47c0ea356ba50b738537adfab (patch)
treec033b1e5fbebf5a4f50ebd8f1a1a3fa3f336fd4a /techlibs/greenpak4
parent01a5f711871658c9997f7352414cd4ac50ed772c (diff)
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Added GP_RCOSC cell
Diffstat (limited to 'techlibs/greenpak4')
-rw-r--r--techlibs/greenpak4/cells_sim.v38
1 files changed, 38 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 1234ce1b2..800fe3ab5 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -118,6 +118,44 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRI
endmodule
+module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
+
+ parameter PWRDN_EN = 0;
+ parameter AUTO_PWRDN = 0;
+ parameter PRE_DIV = 1;
+ parameter FABRIC_DIV = 1;
+ parameter OSC_FREQ = "25k"
+
+ initial CLKOUT_PREDIV = 0;
+ initial CLKOUT_FABRIC = 0;
+
+ //output dividers not implemented for simulation
+ //auto powerdown not implemented for simulation
+
+ always begin
+ if(PWRDN) begin
+ CLKOUT_PREDIV = 0;
+ CLKOUT_FABRIC = 0;
+ end
+ else begin
+
+ if(OSC_FREQ == "25k") begin
+ //half period of 25 kHz
+ #20000;
+ end
+
+ else begin
+ //half period of 2 MHz
+ #250;
+ end
+
+ CLKOUT_PREDIV = ~CLKOUT_PREDIV;
+ CLKOUT_FABRIC = ~CLKOUT_FABRIC;
+ end
+ end
+
+endmodule
+
module GP_COUNT8(input CLK, input wire RST, output reg OUT);
parameter RESET_MODE = "RISING";