iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth_gowin: Add rPLL blackbox	Konrad Beckmann	2020-11-11	1	-0/+45
\|
*	synth_gowin: ABC9 support	Dan Ravensloft	2020-07-05	1	-20/+323
\| \| \| \| \|	This adds ABC9 support for synth_gowin; drastically improving synthesis quality.
*	gowin: Fix INIT values in sim library.	Marcelina Kościelnicka	2020-07-05	1	-8/+8
\|
*	add IOBUF	Pepijn de Vos	2019-10-28	1	-0/+8
\|
*	add tristate buffer and test	Pepijn de Vos	2019-10-28	1	-0/+6
\|
*	add wide luts	Pepijn de Vos	2019-10-28	1	-0/+35
\|
*	ALU sim tweaks	Pepijn de Vos	2019-10-24	1	-11/+11
\|
*	add negedge DFF	Pepijn de Vos	2019-10-21	1	-8/+113
\|
*	use ADDSUB ALU mode to remove inverters	Pepijn de Vos	2019-10-21	1	-4/+74
\|
*	remove duplicate DFFR	Pepijn de Vos	2019-10-16	1	-10/+0
\|
*	Revert "add MUX support"	Pepijn de Vos	2019-09-06	1	-13/+0
\| \| \| \| \| \|	It turns out that they make everything worse and they don't PnR. This reverts commit 3eff2271d0fe25632f7e6b22cf0be078d2cd9990.
*	add more DFF to sim lib	Pepijn de Vos	2019-09-06	1	-0/+105
\|
*	WIP aditional DFF primitives	Pepijn de Vos	2019-09-05	1	-0/+2
\|
*	add MUX support	Pepijn de Vos	2019-09-05	1	-0/+13
\|
*	GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow	Diego	2019-04-12	1	-0/+134
\|
*	Changes in GoWin synth commands and ALU primitive support	Diego H	2018-12-03	1	-0/+6
\|
*	Indenting fixes in gowin sim cell lib	Clifford Wolf	2016-11-08	1	-20/+28
\|
*	Added initial version of "synth_gowin"	Clifford Wolf	2016-11-01	1	-0/+51