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* Fix invalid verilog syntaxMiodrag Milanovic2020-03-141-1/+1
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* Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-031-2/+17
|\ | | | | Add -flowmap option to `synth{,_ice40}`
| * Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-281-2/+17
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* | Create +/abc9_model.v for $__ABC9_{DELAY,FF_}Eddie Hung2020-02-272-0/+11
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* techmap: fix shiftx2mux decompositionEddie Hung2020-02-071-8/+6
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* shiftx2mux: fix select out of boundsEddie Hung2020-02-051-1/+2
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* Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-052-2/+0
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| * abc9_ops: -write_box is empty, output a dummy box to prevent ABC errorEddie Hung2020-01-152-2/+0
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* | Explicitly create separate $mux cellsEddie Hung2020-01-211-2/+2
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* | Fix tests -- when Y_WIDTH is non-pow-2Eddie Hung2020-01-211-3/+4
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* | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-213-73/+69
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* | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-212-0/+39
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* Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Makefile: don't assume python is called `python3`Sean Cross2019-10-191-2/+2
| | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
* Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
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* Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-34/+6
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* mul2dsp.v slice namesEddie Hung2019-09-251-5/+5
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* Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicitEddie Hung2019-09-251-3/+1
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* Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"Eddie Hung2019-09-251-2/+6
| | | | This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1.
* Revert "No need for $__mul anymore?"Eddie Hung2019-09-251-8/+8
| | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827.
* Remove _TECHMAP_CELLTYPE_ check since all $mulEddie Hung2019-09-251-6/+2
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* No need for $__mul anymore?Eddie Hung2019-09-251-8/+8
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* Fix signedness bugEddie Hung2019-09-201-2/+2
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* Be sensitive to signednessEddie Hung2019-09-101-20/+21
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* Really get rid of 'opt_expr -fine' by being explicitEddie Hung2019-09-101-6/+33
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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-052-0/+2
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| * Use a dummy box file if none specifiedEddie Hung2019-08-282-0/+2
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* | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-301-1/+1
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| * | Merge branch 'master' into xc7dspDavid Shah2019-08-301-1/+1
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| | * Missing newlineEddie Hung2019-08-201-1/+1
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* | | Only swap ports if $mul and not $__mulEddie Hung2019-08-131-1/+1
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* | | Add DSP_A_MAXWIDTH_PARTIAL, refactorEddie Hung2019-08-131-144/+110
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* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-121-8/+36
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| * Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
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| * A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
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| * Add more commentsEddie Hung2019-08-091-4/+18
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| * Add a few comments to document $alu and $lcuEddie Hung2019-08-081-9/+12
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* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-071-0/+19
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| * Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+19
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Trim Y_WIDTHEddie Hung2019-08-011-5/+3
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* | Add DSP_SIGNEDONLY backEddie Hung2019-08-011-0/+16
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* | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-011-4/+11
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* | Revert "Do not do sign extension in techmap; let packer do it"Eddie Hung2019-08-011-5/+14
| | | | | | | | This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd.
* | Fix B_WIDTH > DSP_B_MAXWIDTH caseEddie Hung2019-08-011-32/+14
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* | Do not compute sign bit if result is zeroEddie Hung2019-07-311-1/+2
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* | For signed multipliers, compute sign bit separately...Eddie Hung2019-07-311-23/+42
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* | Fix spacingEddie Hung2019-07-261-3/+3
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* | Add copyright header, comment on cascadeEddie Hung2019-07-241-4/+34
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* | Typo for Y_WIDTHEddie Hung2019-07-231-1/+1
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* | Use minimum sized width wiresEddie Hung2019-07-221-7/+13
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