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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-2912-229/+2498
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| * Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2912-229/+2498
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| | * Ooops AREG and BREG to default to -1Eddie Hung2019-09-271-2/+2
| | * Update doc with max cascade chain of 20Eddie Hung2019-09-261-2/+4
| | * Do not always zero out C (e.g. during cascade breaks)Eddie Hung2019-09-262-7/+3
| | * Update docEddie Hung2019-09-261-1/+2
| | * Zero out portsEddie Hung2019-09-261-2/+2
| | * xilinx_dsp_cascade to also cascade AREG and BREGEddie Hung2019-09-262-454/+172
| | * Try recursive pmgen for P cascadeEddie Hung2019-09-261-88/+118
| | * CREG to check for \keepEddie Hung2019-09-261-0/+3
| | * Remove newlineEddie Hung2019-09-261-1/+0
| | * Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)Eddie Hung2019-09-251-1/+5
| | * Reject if (* init *) presentEddie Hung2019-09-252-0/+6
| | * Rework xilinx_dsp postAdd for new wreduce callEddie Hung2019-09-251-3/+3
| | * Fix memory issue since SigSpec& could be invalidatedEddie Hung2019-09-251-6/+10
| | * unextend only used in initEddie Hung2019-09-251-2/+1
| | * Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-251-5/+4
| | * "abc_padding" attr for blackbox outputs that were padded, remove them laterEddie Hung2019-09-231-3/+16
| | * Set [AB]CASCREG to legal valuesEddie Hung2019-09-231-6/+10
| | * Comment to explain separating CREG packingEddie Hung2019-09-231-0/+8
| | * Separate out CREG packing into new pattern, to avoid conflict with PREGEddie Hung2019-09-234-46/+273
| | * Move log_debug("\n") laterEddie Hung2019-09-231-1/+1
| | * Move unextend initialisation laterEddie Hung2019-09-231-12/+9
| | * Use new port() overload once moreEddie Hung2019-09-231-2/+2
| | * Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-231-1/+7
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| | * | Use new port/param overload in pmgEddie Hung2019-09-204-22/+22
| | * | Output pattern matcher items as log_debug()Eddie Hung2019-09-202-31/+27
| | * | OPMODE is port not paramEddie Hung2019-09-201-7/+6
| | * | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-201-0/+18
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| | * | | Do not run xilinx_dsp_cascadeAB for nowEddie Hung2019-09-201-1/+2
| | * | | WIP for xiinx_dsp_cascadeABEddie Hung2019-09-201-3/+499
| | * | | Run until convergenceEddie Hung2019-09-201-3/+9
| | * | | Cleanup ice40_dsp.pmgEddie Hung2019-09-201-12/+6
| | * | | Cleanup xilinx_dspEddie Hung2019-09-201-1/+1
| | * | | More exceptionsEddie Hung2019-09-201-2/+2
| | * | | Update docEddie Hung2019-09-201-2/+2
| | * | | Add a xilinx_dsp_cascade matcher for PCIN -> PCOUTEddie Hung2019-09-204-54/+105
| | * | | Add an overload for port/param with default valueEddie Hung2019-09-201-0/+8
| | * | | Small cleanupEddie Hung2019-09-201-19/+18
| | * | | Disable support for SB_MAC16 reset since it is asyncEddie Hung2019-09-192-3/+7
| | * | | SB_MAC16 ffCD to not pack same as ffOEddie Hung2019-09-191-2/+2
| | * | | ClarifyEddie Hung2019-09-191-1/+2
| | * | | Update doc for ice40_dspEddie Hung2019-09-191-1/+10
| | * | | Add an indexEddie Hung2019-09-192-0/+3
| | * | | Fix width of DEddie Hung2019-09-191-1/+1
| | * | | Use ID() macroEddie Hung2019-09-192-210/+210
| | * | | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-193-5/+173
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| | * | | | Re-enable sign extension for C inputEddie Hung2019-09-191-4/+4
| | * | | | Do not perform width-checks for DSP48E1 which is much more complicatedEddie Hung2019-09-191-11/+0
| | * | | | Remove TODO as check should not be necessaryEddie Hung2019-09-191-1/+0