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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 13:00:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 13:00:44 -0700 |
| commit | a67af3d5e5fd584837f55d2d97d621299e4fdf0c (patch) | |
| tree | 2bcb43b0395c2f5fd50b8cffd04e56d54e54d7eb /passes | |
| parent | bcee87a45768a1650fb7770d301cfeb8e87a1b8d (diff) | |
| download | yosys-a67af3d5e5fd584837f55d2d97d621299e4fdf0c.tar.gz yosys-a67af3d5e5fd584837f55d2d97d621299e4fdf0c.tar.bz2 yosys-a67af3d5e5fd584837f55d2d97d621299e4fdf0c.zip | |
Use new port() overload once more
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index bb29bdd99..80bf775bc 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -38,8 +38,8 @@ code sigA sigB sigC sigD sigM sigA = unextend(port(dsp, \A)); sigB = unextend(port(dsp, \B)); - sigC = dsp->connections_.at(\C, SigSpec()); - sigD = dsp->connections_.at(\D, SigSpec()); + sigC = port(dsp, \C, SigSpec()); + sigD = port(dsp, \D, SigSpec()); SigSpec P = port(dsp, \P); if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") { |